Abstract: In an integrated circuit type dual ramp analog to digital converter (10), the duration of the reference voltage integration, or ramp-down period, is precisely determined to control count accumulation in an external output counter (32a) operating in parallel with the standard internal counter of the integrated circuit. A reference voltage is stored on a flying capacitor (50) that is polarity switched, depending upon the polarity of the input signal, to be applied to the input of an integrator (12) during the ramp-down period. To establish the beginning and end of ramp-down, one end (52) of the flying capacitor (50) is applied to a comparator (54). As the voltage at the monitored end of the flying capacitor (50) undergoes abrupt level changes at the end points of the ramp-down interval, the comparator (54) generates start and stop pulses to the external output counter (32a).

Abstract: An offset circuit for use in providing an offset signal to an analog-to-digital converter. The analog-to-digital converter has an integrator for performing signal integrate operations and is connected to a digital display. The offset circuit is gated to provide a variable offset current directly to the integrator of the analog-to-digital converter, thereby eliminating adverse loading effects on the high input impedance of the analog-to-digital converter.

Abstract: An AC display excitation and synchronous display updating circuit for a digital electronic instrument in which the counter accumulating clock pulses representative of the magnitude of the quantity to be represented on the digital display is used as a frequency divider to obtain an AC display energizing signal whose frequency is reduced from the clock frequency to a suitable level for energizing the display. The contents of the continuously driven counter are synchronously transferred to the display register at the end of the conversion cycle by the use of a two-phase clock.