Abstract: An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure includes an active device. The active device includes a plurality of drains. Each of the drains has a contact row and at least one body contact row. The at least one body contact row is located on the active device in a manner to reduce the amount of voltage required for triggering the ESD protection structure.

Abstract: An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure includes an active device. The active device includes a plurality of drains. Each of the drains has a contact row and at least one body contact row. The at least one body contact row is located on the active device in a manner to reduce the amount of voltage required for triggering the ESD protection structure.

Abstract: An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure includes an active device. The active device includes a plurality of drains. Each of the drains has a contact row and at least one body contact row. The at least one body contact row is located on the active device in a manner to reduce the amount of voltage required for triggering the ESD protection structure.

Abstract: A method of fabricating an electronic device and a resulting electronic device. The method includes forming a pad oxide layer on a substrate, forming a silicon nitride layer over the pad oxide layer, and forming a top oxide layer over the silicon nitride layer. A first dopant region is then formed in a first portion of the substrate. A first portion of the top oxide layer is removed; a remaining portion of the top oxide layer is used to align a second dopant mask and a second dopant region is formed. An annealing step drives-in the dopants but oxygen diffusion to the substrate is limited by the silicon nitride layer; the silicon nitride layer thereby assures that the uppermost surface of the silicon is substantially planar in an area proximate to the dopant regions after the annealing step.

Abstract: A method and system for providing a twin well in a semiconductor device is described. The method and system include masking a first portion of the device such that a second portion of the device is exposed. A sacrificial layer has a first portion on the first portion of the device and a second portion on the second portion of the device. In one aspect, an oxidation stop layer may be below the sacrificial layer. The method and system include implanting a first well in the second portion of the device, exposing the first portion of the device after the first well is implanted, and oxidizing the second portion of sacrificial layer after the exposing. The method and system further include implanting the second well in the first portion of the device after the oxidizing and planarizing the device after the second well is implanted.

Abstract: An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure comprises an active device. The active device includes a plurality of drains. Each of the drains has a contact row and at least one body contact row. The at least one body contact row is located on the active device in a manner to reduce the amount of voltage required for triggering the ESD protection structure. A system and method in accordance with the present invention utilizes a LDNMOS transistor as ESD protection element with optimised substrate contacts. The ratio of substrate contact rows to drain contact rows is smaller than one in order to reduce the triggering voltage of the inherent bipolar transistor.

Abstract: A protective envelope for a chip card wherein a fabric sheath with a top flap allows entry of the chip card. An inner Faraday cage, nested within the fabric sheath, made of wire mesh or thin foil prevents electromagnetic fields from penetrating the sheath once the top flap is closed on the sheath body.