Abstract: In an embodiment, a processor includes at least one functional block and a central power controller. The at least one functional block may include at least one block component and block power logic. The block power logic may be to: receive a first request to initiate a first reduced power mode in the at least one functional block, and in response to the first request, send a notification signal to a central power controller. The central power controller may be to, in response to the notification signal: store a first state of the at least one functional block, and initiate the first reduced power mode in the at least one functional block. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor includes at least one functional block and a central power controller. The at least one functional block may include at least one block component and block power logic. The block power logic may be to: receive a first request to initiate a first reduced power mode in the at least one functional block, and in response to the first request, send a notification signal to a central power controller. The central power controller may be to, in response to the notification signal: store a first state of the at least one functional block, and initiate the first reduced power mode in the at least one functional block. Other embodiments are described and claimed.

Abstract: Embodiments of the invention describe arbitrating requests received from a plurality of agents for memory. Each memory request may indicate a priority level of the memory request and a size of the memory to be accessed. Said requests may be stored in a queue. Arbitration logic, coupled to the plurality of agents and the queue, may receive said memory requests and determine which requests to send to the queue based, at least in part, on the priority of each request and the size of the memory to be accessed by each memory request.

Abstract: Methods and apparatus for supporting programmable burst management schemes on pipelined buses. The apparatus includes a plurality of bus masters (masters), configured in a plurality of clusters, and a plurality of target sub-groups. Each target sub-group includes one or more shared resource targets. A scalable chassis infrastructure is used to interconnect the targets with the clusters using a crossbar interconnect configuration including pipelined command, and data buses. The interconnect includes sub-group multiplexers for each sub-group and sub-group selection multiplexers coupled to each cluster. A two-stage arbiter, operatively coupled to the targets, sub-group multiplexers, and sub-group selection multiplexers, is employed to arbitrate transaction requests issued from the masters to the targets and manage transactions. The two-stage arbiter includes a provision for supporting programmable burst management, wherein selected sub-groups can be tuned for handling short or long burst traffic.

Abstract: A scalable, two-stage round-robin arbiter with re-circulation and bounded latency for use in multi-threaded, multi-processing devices. An apparatus implementing the two-stage arbiter includes a plurality of masters configured in a plurality of clusters, a plurality of targets, and an chassis interconnect that may be controlled to selectively connects a given master to a given target. The chassis interconnect includes multiple sets of bus lines connected between the plurality of clusters and the plurality of targets forming a cross-bar interconnect, including sets of bus lines corresponding to a command bus. A two-stage arbitration scheme is employed to arbitrate access to the command bus. The first arbitration stage is used to arbitrate between command requests issued by masters in a given cluster. The second arbitration stage is used to arbitrate between winning first stage command requests. One embodiment of the arbitration scheme employs re-circulation of second stage losers.

Abstract: A scalable, two-stage rotating priority arbiter with re-circulation and bounded latency for use in multi-threaded, multi-processing devices. An apparatus implementing the two-stage arbiter includes a plurality of masters configured in a plurality of clusters, a plurality of targets, and an chassis interconnect that may be controlled to selectively connects a given master to a given target. The chassis interconnect includes multiple sets of bus lines connected between the plurality of clusters and the plurality of targets forming a cross-bar interconnect, including sets of bus lines corresponding to a command bus. A two-stage arbitration scheme is employed to arbitrate access to the command bus. The first arbitration stage is used to arbitrate between target requests issued by masters in a given cluster. The second arbitration stage is used to arbitrate between winning first-stage target requests. One embodiment of the arbitration scheme employs a rotating priority arbitration scheme at the first stage.

Abstract: A scalable, two-stage round-robin arbiter with re-circulation and bounded latency for use in multi-threaded, multi-processing devices. An apparatus implementing the two-stage arbiter includes a plurality of masters configured in a plurality of clusters, a plurality of targets, and an chassis interconnect that may be controlled to selectively connects a given master to a given target. The chassis interconnect includes multiple sets of bus lines connected between the plurality of clusters and the plurality of targets forming a cross-bar interconnect, including sets of bus lines corresponding to a command bus. A two-stage arbitration scheme is employed to arbitrate access to the command bus. The first arbitration stage is used to arbitrate between command requests issued by masters in a given cluster. The second arbitration stage is used to arbitrate between winning first stage command requests. One embodiment of the arbitration scheme employs re-circulation of second stage losers.

Abstract: Methods and apparatus for supporting programmable burst management schemes on pipelined buses. The apparatus includes a plurality of bus masters (masters), configured in a plurality of clusters, and a plurality of target sub-groups. Each target sub-group includes one or more shared resource targets. A scalable chassis infrastructure is used to interconnect the targets with the clusters using a crossbar interconnect configuration including pipelined command, and data buses. The interconnect includes sub-group multiplexers for each sub-group and sub-group selection multiplexers coupled to each cluster. A two-stage arbiter, operatively coupled to the targets, sub-group multiplexers, and sub-group selection multiplexers, is employed to arbitrate transaction requests issued from the masters to the targets and manage transactions. The two-stage arbiter includes a provision for supporting programmable burst management, wherein selected sub-groups can be tuned for handling short or long burst traffic.