Abstract: Data transfer rates input to and output from electronic devices are a function of I/O pad circuit structure. The load capacitance of an I/O pad may reduce the bandwidth of an I/O circuit. A reduced pad capacitance circuit may be used to reduce or eliminate the positive and physical pad capacitance associated with a capacitive pad. This negative capacitance reduces or minimizes poor signal quality arising from large pad capacitance. This improved signal may be fed into a comparator, where the signal may be improved further using an equalizer. The use of negative capacitance circuit will increase the transmit and receive signaling quality of I/O interfaces.

Abstract: Some embodiments include an apparatus having a conductive pad, a first supply node, a second supply node, and a driver. The driver includes first transistors coupled between the first supply node and a number of nodes, and second transistors coupled between the second node and the number of nodes. The driver also includes circuit paths coupled between the conductive pad and respective nodes of the number of nodes. At least one of the circuit paths includes parallel-connected resistors. At least two of the circuit paths include a single resistor.

Abstract: Data transfer rates input to and output from electronic devices are a function of I/O pad circuit structure. The load capacitance of an I/O pad may reduce the bandwidth of an I/O circuit. A reduced pad capacitance circuit may be used to reduce or eliminate the positive and physical pad capacitance associated with a capacitive pad. This negative capacitance reduces or minimizes poor signal quality arising from large pad capacitance. This improved signal may be fed into a comparator, where the signal may be improved further using an equalizer. The use of negative capacitance circuit will increase the transmit and receive signaling quality of I/O interfaces.