Abstract: In one aspect, the invention comprises an implantable living electrode comprising a substantially cylindrical extracellular matrix core; one or more neurons implanted along or within the substantially cylindrical extracellular matrix core, the one or more neurons including one or more optogenetic or magnetogenetic neurons proximal to a first end of the implantable living electrode.

Abstract: In one aspect, the invention comprises an implantable living electrode comprising a substantially cylindrical extracellular matrix core; one or more neurons implanted along or within the substantially cylindrical extracellular matrix core, the one or more neurons including one or more optogenetic or magnetogenetic neurons proximal to a first end of the implantable living electrode.

Abstract: In various aspects and embodiments the present disclosure provides a construct comprising a pre-formed neural network, the construct comprising a micro-column comprising an outer sheath comprising a hyaluronic acid (HA) hydrogel, and a core comprising an extracellular matrix (ECM); a plurality of neurons within the micro-column. The present disclosure further provides methods of making and using the same.

Abstract: In one aspect, the invention comprises an implantable living electrode comprising a substantially cylindrical extracellular matrix core; one or more neurons implanted along or within the substantially cylindrical extracellular matrix core, the one or more neurons including one or more optogenetic or magnetogenetic neurons proximal to a first end of the implantable living electrode.

Abstract: In one aspect, the invention comprises an implantable living electrode comprising a substantially cylindrical extracellular matrix core; one or more neurons implanted along or within the substantially cylindrical extracellular matrix core, the one or more neurons including one or more optogenetic or magnetogenetic neurons proximal to a first end of the implantable living electrode.

Abstract: The present invention discloses an adaptive phase-shifted synchronization clock generation circuit and a method for generating phase-shifted synchronization clock. The adaptive phase-shifted synchronization clock generation circuit includes: a current source generating a current which flows through a node to generate a node voltage on the node; a reverse-proportional voltage generator coupled to the node for generating a voltage which is reverse-proportional to the node voltage; a ramp generator receiving a synchronization input signal and generating a ramp signal; a comparator comparing the reverse-proportional voltage to the ramp signal; and a pulse generator for generating a clock signal according to an output from the comparator.

Abstract: The present invention discloses an adaptive phase-shifted synchronization clock generation circuit and a method for generating phase-shifted synchronization clock. The adaptive phase-shifted synchronization clock generation circuit includes: a current source generating a current which flows through a node to generate a node voltage on the node; a reverse-proportional voltage generator coupled to the node for generating a voltage which is reverse-proportional to the node voltage; a ramp generator receiving a synchronization input signal and generating a ramp signal; a comparator comparing the reverse-proportional voltage to the ramp signal; and a pulse generator for generating a clock signal according to an output from the comparator.

Abstract: The present invention discloses a digital dimming device and a digital dimming method, for controlling a plurality of light emitting device channels. The method comprises: generating a corresponding plurality of driving signals to control the plurality of light emitting device channels; receiving a PWM input signal having a duty ratio, and phase shifting the PWM input signal to generate multiple PWM output signals with about the same duty ratio as the PWM input signal, but with respectively shifted phases; and enabling or disabling corresponding driving signals by the multiple PWM output signals, respectively.

Abstract: The present invention discloses an adaptive phase-shifted synchronization clock generation circuit and a method for generating phase-shifted synchronization clock. The adaptive phase-shifted synchronization clock generation circuit includes: a current source generating a current which flows through a node to generate a node voltage on the node; a reverse-proportional voltage generator coupled to the node for generating a voltage which is reverse-proportional to the node voltage; a ramp generator receiving a synchronization input signal and generating a ramp signal; a comparator comparing the reverse-proportional voltage to the ramp signal; and a pulse generator for generating a clock signal according to an output from the comparator.

Abstract: The present invention discloses an adaptive phase-shifted synchronization clock generation circuit and a method for generating phase-shifted synchronization clock. The adaptive phase-shifted synchronization clock generation circuit includes: a current source generating a current which flows through a node to generate a node voltage on the node; a reverse-proportional voltage generator coupled to the node for generating a voltage which is reverse-proportional to the node voltage; a ramp generator receiving a synchronization input signal and generating a ramp signal; a comparator comparing the reverse-proportional voltage to the ramp signal; and a pulse generator for generating a clock signal according to an output from the comparator.

Abstract: The present invention discloses a digital dimming device and a digital dimming method, for controlling a plurality of light emitting device channels. The method comprises: generating a corresponding plurality of driving signals to control the plurality of light emitting device channels; receiving a PWM input signal having a duty ratio, and phase shifting the PWM input signal to generate multiple PWM output signals with about the same duty ratio as the PWM input signal, but with respectively shifted phases; and enabling or disabling corresponding driving signals by the multiple PWM output signals, respectively.

Abstract: A circuit and method for soft start of a system compare a feedback signal produced from an output voltage of the system with a ramp signal to generate a comparison signal, and enables the system once the comparison signal indicating the ramp signal reaches the feedback signal, such that the output voltage becomes active from a residual voltage toward a target level.