Patents by Inventor Isaac CHUNG

Isaac CHUNG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Three dimensional semiconductor integrated circuit having gate pick-up line and method of manufacturing the same
    Patent number: 9257487
    Abstract: A 3D semiconductor integrated circuit having a gate pick-up line and a method of manufacturing the same, wherein the semiconductor integrated circuit includes a plurality of active pillars formed in a gate pick-up region, buffer layers formed on the respective active pillars in the gate pick-up region, gates each surrounding an outer circumference of the corresponding active pillar and the corresponding buffer layer, and a gate pick-up line electrically coupled to the gates.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: February 9, 2016
    Assignee: SK Hynix Inc.
    Inventors: Isaac Chung, Jin Ha Kim
  • Three dimensional semiconductor integrated circuit having gate pick-up line and method of manufacturing the same
    Patent number: 9240479
    Abstract: A 3D semiconductor integrated circuit having a gate pick-up line and a method of manufacturing the same, wherein the semiconductor integrated circuit includes a plurality of active pillars formed in a gate pick-up region, buffer layers formed on the respective active pillars in the gate pick-up region, gates each surrounding an outer circumference of the corresponding active pillar and the corresponding buffer layer, and a gate pick-up line electrically coupled to the gates.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: January 19, 2016
    Assignee: SK Hynix Inc.
    Inventors: Isaac Chung, Jin Ha Kim
  • THREE DIMENSIONAL SEMICONDUCTOR INTEGRATED CIRCUIT HAVING GATE PICK-UP LINE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20160005794
    Abstract: A 3D semiconductor integrated circuit having a gate pick-up line and a method of manufacturing the same, wherein the semiconductor integrated circuit includes a plurality of active pillars formed in a gate pick-up region, buffer layers formed on the respective active pillars in the gate pick-up region, gates each surrounding an outer circumference of the corresponding active pillar and the corresponding buffer layer, and a gate pick-up line electrically coupled to the gates.
    Type: Application
    Filed: September 16, 2015
    Publication date: January 7, 2016
    Inventors: Isaac CHUNG, Jin Ha KIM
  • THREE DIMENSIONAL SEMICONDUCTOR INTEGRATED CIRCUIT HAVING GATE PICK-UP LINE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20160005859
    Abstract: A 3D semiconductor integrated circuit having a gate pick-up line and a method of manufacturing the same, wherein the semiconductor integrated circuit includes a plurality of active pillars formed in a gate pick-up region, buffer layers formed on the respective active pillars in the gate pick-up region, gates each surrounding an outer circumference of the corresponding active pillar and the corresponding buffer layer, and a gate pick-up line electrically coupled to the gates.
    Type: Application
    Filed: September 16, 2015
    Publication date: January 7, 2016
    Inventors: Isaac CHUNG, Jin Ha KIM
  • Three dimensional semiconductor integrated circuit having gate pick-up line and method of manufacturing the same
    Patent number: 9166015
    Abstract: A 3D semiconductor integrated circuit having a gate pick-up line and a method of manufacturing the same, wherein the semiconductor integrated circuit includes a plurality of active pillars formed in a gate pick-up region, buffer layers formed on the respective active pillars in the gate pick-up region, gates each surrounding an outer circumference of the corresponding active pillar and the corresponding buffer layer, and a gate pick-up line electrically coupled to the gates.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: October 20, 2015
    Assignee: SK Hynix Inc.
    Inventors: Isaac Chung, Jin Ha Kim
  • THREE DIMENSIONAL SEMICONDUCTOR INTEGRATED CIRCUIT HAVING GATE PICK-UP LINE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20150279952
    Abstract: A 3D semiconductor integrated circuit having a gate pick-up line and a method of manufacturing the same, wherein the semiconductor integrated circuit includes a plurality of active pillars formed in a gate pick-up region, buffer layers formed on the respective active pillars in the gate pick-up region, gates each surrounding an outer circumference of the corresponding active pillar and the corresponding buffer layer, and a gate pick-up line electrically coupled to the gates.
    Type: Application
    Filed: June 12, 2014
    Publication date: October 1, 2015
    Inventors: Isaac CHUNG, Jin Ha KIM