Abstract: A digital to analog converter (DAC) has an adjustable dynamic range. Specifically, the adjustable DAC has a control port that receives a control signal indicative of the dynamic range, and the DAC produces an analog signal of the specified dynamic range in response to a corresponding digital signal. In one embodiment, the adjustable DAC includes a bitstream generator that repeatedly generates a bitstream and a low pass filter that receives and filters the repeated bitstream. The bitstream generator is adjustable, and can produce bitstreams of different lengths, depending on the control signal. Increasing the bitstream length results in a greater dynamic range of the analog signal, and vice versa. A user can use a preexisting filter to perform the low pass filtering, by simply selecting a value of the control signal.

Abstract: A multiprocessor system uses a master processor coupled to a ROM device to transfer boot code to slave processors over a bus. The memory controllers in the slave processors are controlled to deny processor memory request until the boot code has been transferred to their RAM devices. The memory controllers map the transferred boot codes to a first address space in their RAM devices.

Abstract: A method for automatically selecting delays for slave processors' memory controllers in a multiprocessor system is presented. A master processor coupled to the slave processors on a bootstrap bus commands the slave processors' memory controllers to select the delays. Various delay parameters are tested to select optimal delay parameter values.

Abstract: A digital to analog converter (DAC) has an adjustable dynamic range. Specifically, the adjustable DAC has a control port that receives a control signal indicative of the dynamic range, and the DAC produces an analog signal of the specified dynamic range in response to a corresponding digital signal. In one embodiment, the adjustable DAC includes a bitstream generator that repeatedly generates a bitstream and a low pass filter that receives and filters the repeated bitstream. The bitstream generator is adjustable, and can produce bitstreams of different lengths, depending on the control signal. Increasing the bitstream length results in a greater dynamic range of the analog signal, and vice versa. A user can use a preexisting filter to perform the low pass filtering, by simply selecting a value of the control signal.

Abstract: A memory controller configured according to a delay pair for communicating with a memory device automatically selects optimal delay pairs by testing whether successful communication exists at various values for the delay pairs. The resulting set of delay pairs allowing successful communication are divided into a boundary set and non-boundary set. An optimal delay pair from the non-boundary set is chosen according to its relationship to delay pairs in the boundary set.