Abstract: A peripheral controller is provided for controlling communications with one or more peripheral devices. The peripheral controller includes a controller for controlling one or more peripheral devices; and a single interface to a shared memory device that stores configuration information for at least one of the one or more peripheral devices and additional code, such as boot ROM code. The shared memory device may be, for example, an EEPROM or a serial flash memory device. The controller and shared memory device may optionally communicate using a serial bus to further reduce the pin count. A memory controller maps the user addresses into non-overlapping physical addresses within the shared memory device.