Abstract: In one embodiment of the invention, an update circuit having a bus driver to drive a bus dynamically receives an update compensation code. The bus driver receives data at a data clock signal. The update compensation code controls impedance matching at the bus driver according to the data. A code generator generates the update compensation code at a base clock signal. The base clock signal is synchronized with the data clock signal. The base clock signal has an update interval and a quiet interval. A distribution ring interface distributes the update compensation code to the update circuit synchronously with the base clock signal.

Abstract: An active resistor design is adapted to implement a linearized transistor driver that includes a first FET coupled between a supply potential and an output node, with the gate of the first FET being coupled to an input node. Second and third FETs are coupled between the output node and a reference potential, with the gate of the second FET being coupled to the input node.