Abstract: An electronic device configured to perform polar coding is described. The electronic device includes a bit pattern generator (3403) configured to successively perform a bit pattern generation process over a series (t=?n/w?) of clock cycles; and a counter (c, 4203), operably coupled to the bit pattern generator (3403) and configured to count a number of successive bit pattern generation sub-processes over the series (t=?n/w?) of clock cycles. The bit pattern generator (3403) is configured to: provide a successive sub-set of (w) bits from a bit pattern vector (bk,n) in each successive t=?n/w? clock cycle; where the bit pattern vector comprises n bits, of which ‘k’ bits adopt a first binary value and n?k bits adopt a complementary binary value.

Abstract: A polar decoder kernal is described. The polar decoder kernal includes a processing unit having: at least one input configured to receive at least one input Logarithmic Likelihood Ratio, LLR; a logic circuit configured to manipulate the at least one input LLR; and at least one output configured to output the manipulated at least one LLR. The logic circuit of the processing unit includes only a single two-input adder to manipulate the at least one input LLR, and the input LLR and manipulated LLR are in a format of a fixed-point number representation that comprises a two's complement binary number and an additional sign bit.

Abstract: A polar decoder kernal is described. The polar decoder kernal is configured to: receive one or more soft bits from a soft kernal encoded block having a block size of N and output one or more recovered kernal information bits from a recovered kernal information block having a block size of N. The polar decoder kernal comprises a decomposition of a polar code graph into an arbitrary number of columns depending on the kernal block size N.

Abstract: An electronic device configured to perform polar coding is described. The electronic device includes a bit pattern generator (3403) configured to successively perform a bit pattern generation process over a series (t=?n/w?) of clock cycles; and a counter (c, 4203), operably coupled to the bit pattern generator (3403) and configured to count a number of successive bit pattern generation sub-processes over the series (t=?n/w?) of clock cycles. The bit pattern generator (3403) is configured to: provide a successive sub-set of (w) bits from a bit pattern vector (bk,n) in each successive t=?n/w? clock cycle; where the bit pattern vector comprises n bits, of which ‘k’ bits adopt a first binary value and n?k bits adopt a complementary binary value.

Abstract: An electronic device configured to perform polar coding is described. The electronic device includes a bit pattern generator (3403) configured to successively perform a bit pattern generation process over a series (t=?n/w?) of clock cycles; and a counter (c, 4203), operably coupled to the bit pattern generator (3403) and configured to count a number of successive bit pattern generation sub-processes over the series (t=?n/w?) of clock cycles. The bit pattern generator (3403) is configured to: provide a successive sub-set of (w) bits from a bit pattern vector (bk,n) in each successive t=?n/w? clock cycle; where the bit pattern vector comprises n bits, of which ‘k’ bits adopt a first binary value and n?k bits adopt a complementary binary value.

Abstract: A circuit performs a turbo detection process recovering data symbols from a received signal effected, during transmission, by a Markov process with effect that the data symbols are dependent on preceding data symbols represented as a trellis having a plurality of trellis stages. The circuit comprises processing elements, associated with trellis stages representing these dependencies and each configured to receive soft decision values corresponding to associated data symbols Each processing element configured, in one clock cycle to receive data representing a priori forward and backward state metrics, and a priori soft decision values for data symbols detected for the trellis stage. For each clock cycle of the turbo detection process, the circuit processes, for processing elements representing the trellis stages, the a priori information for associated data symbols detected for the trellis stage, and to provide extrinsic soft decision values corresponding to data symbols for a next clock cycle.