Abstract: In accordance with one embodiment, a fan controller operates in a standard mode when main power is provided to the power supply unit in which speed of the fan is controlled in response to a primary pulse width modulation (PWM) signal from a power controller. A loss of the main power to the power supply unit may be detected at a logic circuit, which provides a secondary PWM signal to the fan controller in response to the loss of the main power. In certain embodiments, the fan controller is operated in a power loss mode in response to the secondary PWM signal to direct the speed of the fan to a low-power consumption target speed.

Abstract: An information handling system includes a first device having a first data communication interface connected to a first socket area of a socket. A second device includes a second data communication interface connected to a second socket area of the socket. A host processor includes a third data communication interface connected to a third socket area of the socket. When an interposer is installed into the socket in a first orientation, the interposer connects the first data communication interface to the third data communication interface. When the interposer is installed into the socket in a second orientation, the interposer connects the first data communication interface to the second data communication interface.

Abstract: An information handling system includes a device and a baseboard management controller. The device is configured to communicate with a processor of the information handling system. The baseboard management controller is configured to communicate with the device via an in-band communication channel. The baseboard management controller determines whether data is received from the device via an in-band communication channel, and determines whether the baseboard management controller may communicate with the device via an out-of-band communication channel. In response to the data not being received and the baseboard management controller not able to communicate with the device, the baseboard management controller detects a failure of the device. In response to the detection of the failure of the device, the baseboard management controller isolates the device.

Abstract: An information handling system includes a controller and first, second and third devices. The devices power-on during a power-on sequence of the information handling system. During the power-on sequence, the controller provides a first power brake signal to the first device via a first power brake line, a second power brake signal to the second device via a second power brake line, and a third power brake signal to the third device via a third power brake line. The controller removes the first power brake signal from the first power brake line. In response to an expiration of a first amount of time, the controller removes the second power brake signal from the second power brake line. In response to an expiration of a second amount of time, the controller removes the third power brake signal from the third power brake line.

Abstract: An information handling system includes a processor, a system baseboard management controller (BMC), and a field-programmable gate array (FPGA) add-in card. The FPGA add-in card includes an FPGA and a card BMC. The FPGA is programmed with a plurality of accelerated function units (AFUs) to perform processing tasks for the processor. The card BMC receives a first indication from the system BMC, the first indication to halt a first processing task associated with a first AFU, halts the first processing task in response to the first indication, receives a second AFU from the system BMC, and reprograms the FPGA with the second AFU.

Abstract: An information handling system includes a voltage regulator, a device, and a controller. The voltage regulator provides an output voltage to power on the device. The controller includes a voltage enable sense line. The controller provides a signal to enable the voltage regulator on the voltage enable sense line at a first voltage associated with a first state. The controller also monitors a voltage level on the voltage enable sense line, and determines whether the voltage level of the voltage enable sense line has changed to a second voltage level associated with a second state. In response to the voltage level on the voltage enable sense line changing to the second voltage level, the controller detects that the output voltage is fully turned on and provided to the device.

Abstract: An information handling system includes a first device having a first data communication interface connected to a first socket area of a socket. A second device includes a second data communication interface connected to a second socket area of the socket. A host processor includes a third data communication interface connected to a third socket area of the socket. When an interposer is installed into the socket in a first orientation, the interposer connects the first data communication interface to the third data communication interface. When the interposer is installed into the socket in a second orientation, the interposer connects the first data communication interface to the second data communication interface.

Abstract: An information handling system includes first and second devices, a connectivity switch, and a baseboard management controller. The first and second devices are configured to communicate with first and second processors of the information handling system. The connectivity switch is connected between the first and second devices and the first and second processors. The connectivity switch operates in one of a plurality of configurations including a first configuration, a second configuration, and a third configuration. Each of the configurations provides a different connectivity between the first device, the second device, the first processor, and the second processor. The baseboard management controller determines a setup of the first and second devices, and provides a connectivity indication signal to the connectivity switch based on the setup of the first and second devices. The connectivity indication signal identifies one of the configurations for the connectivity switch.

Abstract: A processing system interconnect link training system includes a processing system that includes a secondary processing subsystem that is coupled to a first primary processing subsystem and a second primary processing system which are coupled to each other via a processing system interconnect that includes a plurality of processing system links. The secondary processing subsystem trains, during a boot operation and according to a first link configuration, the plurality of processing system links. Then the secondary processing subsystem determines that the training of the plurality of processing system links fails and, in response, retrains the plurality of processing system links according to a second link configuration that is a downgraded configuration relative to the first link configuration.

Abstract: A processing system interconnect link training system includes a processing system that includes a secondary processing subsystem that is coupled to a first primary processing subsystem and a second primary processing system which are coupled to each other via a processing system interconnect that includes a plurality of processing system links. The secondary processing subsystem trains, during a boot operation and according to a first link configuration, the plurality of processing system links. Then the secondary processing subsystem determines that the training of the plurality of processing system links fails and, in response, retrains the plurality of processing system links according to a second link configuration that is a downgraded configuration relative to the first link configuration.