Patents by Inventor Isaac Rivera

Isaac Rivera has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CHIP INTEGRATION INTO CAVITIES OF A HOST WAFER USING LATERAL DIELECTRIC MATERIAL BONDING
    Publication number: 20250218882
    Abstract: An electronic assembly has a backside capping layer, a host wafer having a back surface bonded to a top surface of the backside capping layer except for cavities in the wafer formed over areas of the backside capping layer, the cavities having side surfaces of the wafer. Chiplets have backsides bonded directly to at least portion of the areas of the top surface of the backside capping layer. A lateral dielectric material between side surfaces of the chiplets and side surfaces of the wafer, mechano-chemically bonds the side surfaces of the chiplets to the side surfaces of the wafer.
    Type: Application
    Filed: March 3, 2025
    Publication date: July 3, 2025
    Inventors: Florian Herrault, Isaac Rivera, Daniel S. Green, James F. Buckwalter
  • Chip integration into cavities of a host wafer using lateral dielectric material bonding
    Patent number: 12261091
    Abstract: An electronic assembly has a backside capping layer, a host wafer having a back surface bonded to a top surface of the backside capping layer except for cavities in the wafer formed over areas of the backside capping layer, the cavities having side surfaces of the wafer. Chiplets have backsides bonded directly to at least portion of the areas of the top surface of the backside capping layer. A lateral dielectric material between side surfaces of the chiplets and side surfaces of the wafer, mechano-chemically bonds the side surfaces of the chiplets to the side surfaces of the wafer.
    Type: Grant
    Filed: June 12, 2023
    Date of Patent: March 25, 2025
    Assignee: PseudolithIC, Inc.
    Inventors: Florian Herrault, Isaac Rivera, Daniel S. Green, James F. Buckwalter
  • Chip integration into cavities of a host wafer using lateral dielectric material bonding
    Patent number: 12125759
    Abstract: An electronic assembly has a backside capping layer, a host wafer having a back surface bonded to a top surface of the backside capping layer except for cavities in the wafer formed over areas of the backside capping layer, the cavities having side surfaces of the wafer. Chiplets have backsides bonded directly to at least portion of the areas of the top surface of the backside capping layer. A lateral dielectric material between side surfaces of the chiplets and side surfaces of the wafer, mechano-chemically bonds the side surfaces of the chiplets to the side surfaces of the wafer.
    Type: Grant
    Filed: June 12, 2023
    Date of Patent: October 22, 2024
    Assignee: PseudolithIC, Inc.
    Inventors: Florian Herrault, Isaac Rivera, Daniel S. Green, James F. Buckwalter
  • CHIP INTEGRATION INTO CAVITIES OF A HOST WAFER USING LATERAL DIELECTRIC MATERIAL BONDING
    Publication number: 20240243026
    Abstract: An electronic assembly has a backside capping layer, a host wafer having a back surface bonded to a top surface of the backside capping layer except for cavities in the wafer formed over areas of the backside capping layer, the cavities having side surfaces of the wafer. Chiplets have backsides bonded directly to at least portion of the areas of the top surface of the backside capping layer. A lateral dielectric material between side surfaces of the chiplets and side surfaces of the wafer, mechano-chemically bonds the side surfaces of the chiplets to the side surfaces of the wafer.
    Type: Application
    Filed: June 12, 2023
    Publication date: July 18, 2024
    Inventors: Florian Herrault, Isaac Rivera, Daniel S. Green, James F. Buckwalter
  • CHIP INTEGRATION INTO CAVITIES OF A HOST WAFER USING LATERAL DIELECTRIC MATERIAL BONDING
    Publication number: 20240243025
    Abstract: An electronic assembly has a backside capping layer, a host wafer having a back surface bonded to a top surface of the backside capping layer except for cavities in the wafer formed over areas of the backside capping layer, the cavities having side surfaces of the wafer. Chiplets have backsides bonded directly to at least portion of the areas of the top surface of the backside capping layer. A lateral dielectric material between side surfaces of the chiplets and side surfaces of the wafer, mechano-chemically bonds the side surfaces of the chiplets to the side surfaces of the wafer.
    Type: Application
    Filed: June 12, 2023
    Publication date: July 18, 2024
    Inventors: Florian Herrault, Isaac Rivera, Daniel S. Green, James F. Buckwalter
  • Chip integration into cavities of a host wafer using lateral dielectric material bonding
    Patent number: 11756848
    Abstract: An electronic assembly has a backside capping layer, a host wafer having a back surface bonded to a top surface of the backside capping layer except for cavities in the wafer formed over areas of the backside capping layer, the cavities having side surfaces of the wafer. Chiplets have backsides bonded directly to at least portion of the areas of the top surface of the backside capping layer. A lateral dielectric material between side surfaces of the chiplets and side surfaces of the wafer, mechano-chemically bonds the side surfaces of the chiplets to the side surfaces of the wafer.
    Type: Grant
    Filed: January 17, 2023
    Date of Patent: September 12, 2023
    Assignee: PseudolithIC, Inc.
    Inventors: Florian Herrault, Isaac Rivera, Daniel S. Green, James F. Buckwalter