Patents by Inventor Isaac Robin Abothu

Isaac Robin Abothu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7977758
    Abstract: Disclosed are ferroelectric and ferromagnetic noise isolation structures that reduce electromagnetic interference and noise in integrated circuit devices and system architectures. Representative structures comprise two or more devices that are vertically disposed relative to one another, and a thin ferroelectric or ferromagnetic film layer disposed between the respective devices that isolates electromagnetic energy coupling from one device to another.
    Type: Grant
    Filed: June 20, 2008
    Date of Patent: July 12, 2011
    Assignee: Georgia Tech Research Corporation
    Inventors: Markondeya Raj Pulugurtha, Madhaven Swaminathan, Mahadevan Krishna Iyer, Rao Tummala, Isaac Robin Abothu, Jin Hyun Hwang
  • Publication number: 20100103639
    Abstract: Disclosed are ferroelectric and ferromagnetic noise isolation structures that reduce electromagnetic interference and noise in integrated circuit devices and system architectures. Representative structures comprise two or more devices that are vertically disposed relative to one another, and a thin ferroelectric or ferromagnetic film layer disposed between the respective devices that isolates electromagnetic energy coupling from one device to another.
    Type: Application
    Filed: June 20, 2008
    Publication date: April 29, 2010
    Inventors: Markondeya Raj Pulugurtha, Jin Hyun Hwang, Isaac Robin Abothu, Mahadevan Krishna Iyer, Rao Tummala, Madhavan Swaminathan
  • Patent number: 7556189
    Abstract: Nano-structured interconnect formation and a reworkable bonding process using solder films. Large area fabrication of nano-structured interconnects is demonstrated at a very fine pitch. This technology can be used for pushing the limits of current flip chip bonding in terms of pitch, number of I/Os, superior combination of electrical and mechanical properties as well as reworkability. Sol-gel and electroless processes were developed to demonstrate film bonding interfaces between metallic pads and nano interconnects. Solution-derived nano-solder technology is an attractive low-cost method for several applications such as MEMS hermetic packaging, compliant interconnect bonding and bump-less nano-interconnects.
    Type: Grant
    Filed: May 26, 2005
    Date of Patent: July 7, 2009
    Assignee: Georgia Tech Research Corporation
    Inventors: Ankur Aggarwal, Isaac Robin Abothu, Pulugurtha Markondeya Raj, Rao R. Tummala