Abstract: An abnormal current protection device includes an overcurrent protector and a controller, and the overcurrent protector includes a short-circuit detection unit and an overcurrent detection unit. The short-circuit detection unit is configured to detect whether there is a short-circuit event within a period of debounce time of a protection cycle. The overcurrent detection unit is configured to detect whether there is an overcurrent event after the period of debounce time within the protection cycle. The controller is configured to disable a converter when the short-circuit event is detected, and disable a power stage when the overcurrent event is detected.

Abstract: An electronic device includes a sampling circuit and a summing circuit coupled with the sampling circuit. The sampling circuit samples a pulse width of a first input pulse of a PWM input signal since a first time point on a rising edge of a clock pulse of a clock signal. The summing circuit generates a first output pulse of a PWM output signal since a second time point on a falling edge of the clock pulse. A pulse width of the first output pulse is a summation of the pulse width of the first input pulse and a pulse width of a second input pulse of the PWM input signal, and the second input pulse is the next pulse after the first input pulse.

Abstract: A load detection device includes a signal output circuit, comparison circuit, sensing circuit, detection circuit, logic circuit, and control circuit. The signal output circuit outputs a forced current, and generates a bias signal, a first output signal, a second output signal, and a feedback signal depending on the forced current. The comparison circuit compares the reference signal output with the first and second output signals to generate an accurate comparison output for indicating the load state. The sensing circuit generates a sensing signal according to the feedback signal. The detection circuit generates a rough detection output for indicating the load state according to the sensing signal and the first and second output signals. The logic circuit obtains the load state according to the precise comparison output and the rough detection output. The control circuit enables the signal output circuit, comparison circuit, sensing circuit, and logic circuit.

Abstract: An electronic device and a method for overcurrent detection are disclosed herein. The electronic device causes a high-side offsetting voltage drop and converts a voltage difference between a first voltage at an input terminal of an upper-bridge power component of a power stage and a sum of a first balancing voltage drop and the high-side offsetting voltage drop into a first current. The electronic device further converts a voltage difference between a second voltage of an output terminal of the upper-bridge power component and a second balancing voltage drop into a second current, compares the first current and the second current, and generates a high-side overcurrent protection (OCP) signal with logic high for a driver of the power stage when the first current is stronger than the second current, such that the driver turns off the upper-bridge power component accordingly.

Abstract: An abnormal current protection device includes an overcurrent protector and a controller, and the overcurrent protector includes a short-circuit detection unit and an overcurrent detection unit. The short-circuit detection unit is configured to detect whether there is a short-circuit event within a period of debounce time of a protection cycle. The overcurrent detection unit is configured to detect whether there is an overcurrent event after the period of debounce time within the protection cycle. The controller is configured to disable a converter when the short-circuit event is detected, and disable a power stage when the overcurrent event is detected.

Abstract: An electronic device includes a sampling circuit and a summing circuit coupled with the sampling circuit. The sampling circuit samples a pulse width of a first input pulse of a PWM input signal since a first time point on a rising edge of a clock pulse of a clock signal. The summing circuit generates a first output pulse of a PWM output signal since a second time point on a falling edge of the clock pulse. A pulse width of the first output pulse is a summation of the pulse width of the first input pulse and a pulse width of a second input pulse of the PWM input signal, and the second input pulse is the next pulse after the first input pulse.

Abstract: An audio amplifier includes a plurality of power stages, a driving circuit, and a power stage control circuit. The driving circuit is arranged to drive the power stages. The power stage control circuit includes a feedback circuit and a control circuit. The feedback circuit is coupled to the power stages, and is arranged to generate a feedback signal according to at least one detection input, wherein the at least one detection input includes at least one of a power, a voltage signal corresponding to a switching time of the power stages, and a voltage signal corresponding to a switching frequency of the power stages. The control circuit is coupled between the feedback circuit and the power stages, and is arranged to generate a control signal according to the feedback signal, wherein the control signal is arranged to dynamically control a number of turned-on power stages in the power stages.

Abstract: An integrated circuit die forming method, for forming a plurality of integrated circuit dies on a semiconductor wafer, comprising: forming a first device, a second device in a first die in a first area; forming a metal layer connected to the first device and the second device; forming a third device, a fourth device in a second die in a second area; forming the metal layer connected to the third device and the fourth device, wherein a scribe area exists between the first area and the second area is separated by; wherein the first device and the third device are used for synchronization and are components of a class D amplifier; wherein the second device is used for preventing leakage currents of the first die and the fourth device is used for preventing leakage currents of the second die.

Abstract: A low delay time power converter circuit includes a driver circuit and a load. The driver circuit generates a switching driving signal to control the load. The driver circuit includes a switching control circuit and an output stage circuit which includes a first power switch, a second power switch and an impedance adjusting circuit. When the switching control circuit controls the switching driving signal to a first voltage level at a first time point, the first power switch is turned ON and then is turned OFF after a predetermined period. When the switching control circuit controls the switching driving signal to a second voltage level at a second time point, the second power switch is turned ON. The time point when the first power switch is turned OFF is earlier than the second time point. A resistance of the impedance adjusting circuit is larger than a conductive resistance of the first power switch.

Abstract: A dimmer interface circuit includes a buffer stage circuit and a PWM control circuit. The buffer stage circuit converts a dimming input signal to a dimming buffer signal. The buffer stage circuit includes: a power rail generation circuit, which generates a power rail according to the dimming input signal adaptively, so that the dimming input signal is between a high level voltage and a low level voltage of the power rail; and an amplification circuit, which receives the dimming input signal, to generate the dimming buffer signal. The power rail supplies electrical power to the amplification circuit, wherein the amplification circuit operates within a range between the high level voltage and the low level voltage. The PWM control circuit converts the dimming buffer signal to a PWM dimming signal, so as to adjust a brightness of an LED module.

Abstract: A current sensing circuit having self-calibration includes two leads, a sensing element having a sensing resistance, and a sensing and calibration circuit. The sensing and calibration circuit senses and calibrates a sensing voltage of the sensing element, and senses a sensing current through the sensing element according to the sensing resistance and the sensing voltage, to generate a current sensing output signal. The sensing and calibration circuit includes two pads, a V2I circuit, a current mirror circuit and an I2V circuit. The sensing element has a first temperature coefficient (TC). The TC and/or the resistance of an adjusting resistor in the V2I circuit and an adjusting resistor in the I2V circuit are determined according to the first TC, such that the TC of the current sensing output signal is equal to 0.

Abstract: A current sensing circuit having self-calibration includes two leads, a sensing element having a sensing resistance, and a sensing and calibration circuit. The sensing and calibration circuit senses and calibrates a sensing voltage of the sensing element, and senses a sensing current through the sensing element according to the sensing resistance and the sensing voltage, to generate a current sensing output signal. The sensing and calibration circuit includes two pads, a V2I circuit, a current mirror circuit and an I2V circuit. The sensing element has a first temperature coefficient (TC). The TC and/or the resistance of an adjusting resistor in the V2I circuit and an adjusting resistor in the I2V circuit are determined according to the first TC, such that the TC of the current sensing output signal is equal to 0.

Abstract: A dimmer interface circuit includes a buffer stage circuit and a PWM control circuit. The buffer stage circuit converts a dimming input signal to a dimming buffer signal. The buffer stage circuit includes: a power rail generation circuit, which generates a power rail according to the dimming input signal adaptively, so that the dimming input signal is between a high level voltage and a low level voltage of the power rail; and an amplification circuit, which receives the dimming input signal, to generate the dimming buffer signal. The power rail supplies electrical power to the amplification circuit, wherein the amplification circuit operates within a range between the high level voltage and the low level voltage. The PWM control circuit converts the dimming buffer signal to a PWM dimming signal, so as to adjust a brightness of an LED module.

Abstract: A low delay time power converter circuit includes a driver circuit and a load. The driver circuit generates a switching driving signal to control the load. The driver circuit includes a switching control circuit and an output stage circuit which includes a first power switch, a second power switch and an impedance adjusting circuit. When the switching control circuit controls the switching driving signal to a first voltage level at a first time point, the first power switch is turned ON and then is turned OFF after a predetermined period. When the switching control circuit controls the switching driving signal to a second voltage level at a second time point, the second power switch is turned ON. The time point when the first power switch is turned OFF is earlier than the second time point. A resistance of the impedance adjusting circuit is larger than a conductive resistance of the first power switch.

Abstract: An output stage circuit for transmitting data via a bus includes a high side switch, a high side diode structure, a high side clamp circuit, a low side switch, and a low side diode structure. An impedance circuit of the bus is coupled between the high side switch and the low side switch, for generating a differential output signal according to high and low side output signals. A high side N-type region of the high side diode structure encompasses a high side P-type region thereof, and a low side N-type region of the low side diode structure encompasses a low side P-type region thereof. The high side clamp circuit is connected to the high side N-type region in series, for clamping a voltage of the high side N-type region to be not lower than a predetermined voltage, to prevent a parasitic PNP bipolar junction transistor from being turned ON.

Abstract: AN LED driving apparatus includes a power stage circuit and a dimming control circuit. The power stage circuit drives an LED circuit. The dimming control circuit includes a duty ratio conversion circuit, a digital-to analog conversion (DAC) circuit, an error amplifier (EA) circuit and a modulation control circuit. The duty ratio conversion circuit converts a PWM dimming signal to a digital duty ratio signal. The DAC circuit converts the digital duty ratio signal to an analog reference signal. The EA circuit generates an error amplified signal according to a difference between the analog reference signal and an output current related signal. The modulation control circuit generates a PWM control signal according to the error amplified signal, to control the power switch, such that the output current relates to a dimming duty ratio, whereby the dimming control circuit dims the LED circuit according to the PWM dimming signal.

Abstract: AN LED driving apparatus includes a power stage circuit and a dimming control circuit. The power stage circuit drives an LED circuit. The dimming control circuit includes a duty ratio conversion circuit, a digital-to analog conversion (DAC) circuit, an error amplifier (EA) circuit and a modulation control circuit. The duty ratio conversion circuit converts a PWM dimming signal to a digital duty ratio signal. The DAC circuit converts the digital duty ratio signal to an analog reference signal. The EA circuit generates an error amplified signal according to a difference between the analog reference signal and an output current related signal. The modulation control circuit generates a PWM control signal according to the error amplified signal, to control the power switch, such that the output current relates to a dimming duty ratio, whereby the dimming control circuit dims the LED circuit according to the PWM dimming signal.

Abstract: An output stage circuit for transmitting data via a bus includes a high side switch, a high side diode structure, a high side clamp circuit, a low side switch, and a low side diode structure. An impedance circuit of the bus is coupled between the high side switch and the low side switch, for generating a differential output signal according to high and low side output signals. A high side N-type region of the high side diode structure encompasses a high side P-type region thereof, and a low side N-type region of the low side diode structure encompasses a low side P-type region thereof. The high side clamp circuit is connected to the high side N-type region in series, for clamping a voltage of the high side N-type region to be not lower than a predetermined voltage, to prevent a parasitic PNP bipolar junction transistor from being turned ON.

Abstract: A power supply apparatus having multiple output ports includes: a master power supply circuit for supplying a master output power via a master power switch; a slave power supply circuit for supplying a slave output power via a slave power switch; and a shared resistor coupled between a power management node and a reference ground level. The slave sensing circuit outputs the slave sensing current via a slave power management pin, to generate a total power signal at the power management node. The master control circuit senses the total power signal via the master power management pin, to determine an adjustment current. The slave control circuit controls the slave power switch according to a voltage at the slave power management pin, to adjust the slave output power, so that a total power of the master output power and the slave output power does not exceed a predetermined power range.

Abstract: Whether a synchronous signal includes a synchronous pulse is determined by detecting whether there is a positive pulse higher than a positive threshold followed by a negative pulse lower than a negative threshold. The pulse signal detection method includes: comparing the synchronous signal with the positive threshold; comparing the synchronous signal with the negative threshold; and determining that the synchronous pulse exists when the positive pulse of the synchronous signal is higher than the positive threshold and the negative pulse of the synchronous signal is lower than the negative threshold in a post detection period after the positive pulse of the synchronous signal is determined higher than the positive threshold.