Abstract: An integrated circuit die forming method, for forming a plurality of integrated circuit dies on a semiconductor wafer, comprising: forming a first device, a second device in a first die in a first area; forming a metal layer connected to the first device and the second device; forming a third device, a fourth device in a second die in a second area; forming the metal layer connected to the third device and the fourth device, wherein a scribe area exists between the first area and the second area is separated by; wherein the first device and the third device are used for synchronization and are components of a class D amplifier; wherein the second device is used for preventing leakage currents of the first die and the fourth device is used for preventing leakage currents of the second die.

Abstract: A low delay time power converter circuit includes a driver circuit and a load. The driver circuit generates a switching driving signal to control the load. The driver circuit includes a switching control circuit and an output stage circuit which includes a first power switch, a second power switch and an impedance adjusting circuit. When the switching control circuit controls the switching driving signal to a first voltage level at a first time point, the first power switch is turned ON and then is turned OFF after a predetermined period. When the switching control circuit controls the switching driving signal to a second voltage level at a second time point, the second power switch is turned ON. The time point when the first power switch is turned OFF is earlier than the second time point. A resistance of the impedance adjusting circuit is larger than a conductive resistance of the first power switch.

Abstract: A dimmer interface circuit includes a buffer stage circuit and a PWM control circuit. The buffer stage circuit converts a dimming input signal to a dimming buffer signal. The buffer stage circuit includes: a power rail generation circuit, which generates a power rail according to the dimming input signal adaptively, so that the dimming input signal is between a high level voltage and a low level voltage of the power rail; and an amplification circuit, which receives the dimming input signal, to generate the dimming buffer signal. The power rail supplies electrical power to the amplification circuit, wherein the amplification circuit operates within a range between the high level voltage and the low level voltage. The PWM control circuit converts the dimming buffer signal to a PWM dimming signal, so as to adjust a brightness of an LED module.

Abstract: A current sensing circuit having self-calibration includes two leads, a sensing element having a sensing resistance, and a sensing and calibration circuit. The sensing and calibration circuit senses and calibrates a sensing voltage of the sensing element, and senses a sensing current through the sensing element according to the sensing resistance and the sensing voltage, to generate a current sensing output signal. The sensing and calibration circuit includes two pads, a V2I circuit, a current mirror circuit and an I2V circuit. The sensing element has a first temperature coefficient (TC). The TC and/or the resistance of an adjusting resistor in the V2I circuit and an adjusting resistor in the I2V circuit are determined according to the first TC, such that the TC of the current sensing output signal is equal to 0.

Abstract: A current sensing circuit having self-calibration includes two leads, a sensing element having a sensing resistance, and a sensing and calibration circuit. The sensing and calibration circuit senses and calibrates a sensing voltage of the sensing element, and senses a sensing current through the sensing element according to the sensing resistance and the sensing voltage, to generate a current sensing output signal. The sensing and calibration circuit includes two pads, a V2I circuit, a current mirror circuit and an I2V circuit. The sensing element has a first temperature coefficient (TC). The TC and/or the resistance of an adjusting resistor in the V2I circuit and an adjusting resistor in the I2V circuit are determined according to the first TC, such that the TC of the current sensing output signal is equal to 0.

Abstract: A dimmer interface circuit includes a buffer stage circuit and a PWM control circuit. The buffer stage circuit converts a dimming input signal to a dimming buffer signal. The buffer stage circuit includes: a power rail generation circuit, which generates a power rail according to the dimming input signal adaptively, so that the dimming input signal is between a high level voltage and a low level voltage of the power rail; and an amplification circuit, which receives the dimming input signal, to generate the dimming buffer signal. The power rail supplies electrical power to the amplification circuit, wherein the amplification circuit operates within a range between the high level voltage and the low level voltage. The PWM control circuit converts the dimming buffer signal to a PWM dimming signal, so as to adjust a brightness of an LED module.

Abstract: A low delay time power converter circuit includes a driver circuit and a load. The driver circuit generates a switching driving signal to control the load. The driver circuit includes a switching control circuit and an output stage circuit which includes a first power switch, a second power switch and an impedance adjusting circuit. When the switching control circuit controls the switching driving signal to a first voltage level at a first time point, the first power switch is turned ON and then is turned OFF after a predetermined period. When the switching control circuit controls the switching driving signal to a second voltage level at a second time point, the second power switch is turned ON. The time point when the first power switch is turned OFF is earlier than the second time point. A resistance of the impedance adjusting circuit is larger than a conductive resistance of the first power switch.

Abstract: An output stage circuit for transmitting data via a bus includes a high side switch, a high side diode structure, a high side clamp circuit, a low side switch, and a low side diode structure. An impedance circuit of the bus is coupled between the high side switch and the low side switch, for generating a differential output signal according to high and low side output signals. A high side N-type region of the high side diode structure encompasses a high side P-type region thereof, and a low side N-type region of the low side diode structure encompasses a low side P-type region thereof. The high side clamp circuit is connected to the high side N-type region in series, for clamping a voltage of the high side N-type region to be not lower than a predetermined voltage, to prevent a parasitic PNP bipolar junction transistor from being turned ON.

Abstract: AN LED driving apparatus includes a power stage circuit and a dimming control circuit. The power stage circuit drives an LED circuit. The dimming control circuit includes a duty ratio conversion circuit, a digital-to analog conversion (DAC) circuit, an error amplifier (EA) circuit and a modulation control circuit. The duty ratio conversion circuit converts a PWM dimming signal to a digital duty ratio signal. The DAC circuit converts the digital duty ratio signal to an analog reference signal. The EA circuit generates an error amplified signal according to a difference between the analog reference signal and an output current related signal. The modulation control circuit generates a PWM control signal according to the error amplified signal, to control the power switch, such that the output current relates to a dimming duty ratio, whereby the dimming control circuit dims the LED circuit according to the PWM dimming signal.

Abstract: AN LED driving apparatus includes a power stage circuit and a dimming control circuit. The power stage circuit drives an LED circuit. The dimming control circuit includes a duty ratio conversion circuit, a digital-to analog conversion (DAC) circuit, an error amplifier (EA) circuit and a modulation control circuit. The duty ratio conversion circuit converts a PWM dimming signal to a digital duty ratio signal. The DAC circuit converts the digital duty ratio signal to an analog reference signal. The EA circuit generates an error amplified signal according to a difference between the analog reference signal and an output current related signal. The modulation control circuit generates a PWM control signal according to the error amplified signal, to control the power switch, such that the output current relates to a dimming duty ratio, whereby the dimming control circuit dims the LED circuit according to the PWM dimming signal.

Abstract: An output stage circuit for transmitting data via a bus includes a high side switch, a high side diode structure, a high side clamp circuit, a low side switch, and a low side diode structure. An impedance circuit of the bus is coupled between the high side switch and the low side switch, for generating a differential output signal according to high and low side output signals. A high side N-type region of the high side diode structure encompasses a high side P-type region thereof, and a low side N-type region of the low side diode structure encompasses a low side P-type region thereof. The high side clamp circuit is connected to the high side N-type region in series, for clamping a voltage of the high side N-type region to be not lower than a predetermined voltage, to prevent a parasitic PNP bipolar junction transistor from being turned ON.

Abstract: A power supply apparatus having multiple output ports includes: a master power supply circuit for supplying a master output power via a master power switch; a slave power supply circuit for supplying a slave output power via a slave power switch; and a shared resistor coupled between a power management node and a reference ground level. The slave sensing circuit outputs the slave sensing current via a slave power management pin, to generate a total power signal at the power management node. The master control circuit senses the total power signal via the master power management pin, to determine an adjustment current. The slave control circuit controls the slave power switch according to a voltage at the slave power management pin, to adjust the slave output power, so that a total power of the master output power and the slave output power does not exceed a predetermined power range.

Abstract: Whether a synchronous signal includes a synchronous pulse is determined by detecting whether there is a positive pulse higher than a positive threshold followed by a negative pulse lower than a negative threshold. The pulse signal detection method includes: comparing the synchronous signal with the positive threshold; comparing the synchronous signal with the negative threshold; and determining that the synchronous pulse exists when the positive pulse of the synchronous signal is higher than the positive threshold and the negative pulse of the synchronous signal is lower than the negative threshold in a post detection period after the positive pulse of the synchronous signal is determined higher than the positive threshold.

Abstract: A power supply apparatus having multiple output ports includes: a master power supply circuit for supplying a master output power via a master power switch; a slave power supply circuit for supplying a slave output power via a slave power switch; and a shared resistor coupled between a power management node and a reference ground level. The slave sensing circuit outputs the slave sensing current via a slave power management pin, to generate a total power signal at the power management node. The master control circuit senses the total power signal via the master power management pin, to determine an adjustment current. The slave control circuit controls the slave power switch according to a voltage at the slave power management pin, to adjust the slave output power, so that a total power of the master output power and the slave output power does not exceed a predetermined power range.

Abstract: A memory circuit includes a memory unit, a memory control circuit and a pseudo ground voltage generation circuit. The memory control circuit includes: a level shifter circuit coupled to a variable supply voltage; a driver circuit coupled to the pseudo ground voltage generation circuit at the pseudo ground node. The driver circuit is powered by the variable supply voltage and generates an access signal according to the driving signal, to access data from the memory unit. Under a high-voltage operation, the variable supply voltage provides a first supply voltage level, so that a high level of the access signal corresponds to the first supply voltage level and the pseudo ground voltage generation circuit provides a pseudo ground voltage level at the pseudo ground node. A voltage difference between the first supply voltage level and the pseudo ground voltage level is smaller than a withstand voltage of the driver circuit.

Abstract: Whether a synchronous signal includes a synchronous pulse is determined by detecting whether there is a positive pulse higher than a positive threshold followed by a negative pulse lower than a negative threshold. The pulse signal detection method includes: comparing the synchronous signal with the positive threshold; comparing the synchronous signal with the negative threshold; and determining that the synchronous pulse exists when the positive pulse of the synchronous signal is higher than the positive threshold and the negative pulse of the synchronous signal is lower than the negative threshold in a post detection period after the positive pulse of the synchronous signal is determined higher than the positive threshold.

Abstract: A transmission interface with noise reduction function includes a first circuit and a second circuit, for transmitting a signal from the first circuit to the second circuit or from the second circuit to the first circuit. The first circuit includes a first sub-winding and a first wire unit, and the second circuit includes a second sub-winding and a second wire unit. When an electromagnetic noise passes through the first sub-winding and the first wire unit, two loop currents are respectively generated, and the currents have opposite directions to cancel each other so as to reduce the electromagnetic noise. Or, when an emitting current corresponding to the signal flows through the first sub-winding and the first wire unit, two magnetic fields are respectively generated, and the magnetic fields have opposite directions to cancel each other so as to reduce the electromagnetic interference.

Abstract: A memory circuit includes a memory unit, a memory control circuit and a pseudo ground voltage generation circuit. The memory control circuit includes: a level shifter circuit coupled to a variable supply voltage; a driver circuit coupled to the pseudo ground voltage generation circuit at the pseudo ground node. The driver circuit is powered by the variable supply voltage and generates an access signal according to the driving signal, to access data from the memory unit. Under a high-voltage operation, the variable supply voltage provides a first supply voltage level, so that a high level of the access signal corresponds to the first supply voltage level and the pseudo ground voltage generation circuit provides a pseudo ground voltage level at the pseudo ground node. A voltage difference between the first supply voltage level and the pseudo ground voltage level is smaller than a withstand voltage of the driver circuit.

Abstract: A discrete-time current sense circuit includes: a current mirror circuit, which includes: a power switch, for providing the communication current; and a sampling switch, which is for sampling the communication protocol current in a sampling period in a discrete manner, to generate a sampling current; a bias circuit, for providing a reference voltage to the reference node in the sampling period according to a communication protocol voltage of the communication protocol voltage node; a signal conversion circuit, for generating the discrete-time current sense signal according to the sampling current; and a first switch, for operating to determine the sampling period; wherein the sampling period is part of a complete period in which the power switch provides the communication protocol current.

Abstract: The invention provides a power conversion device, including: a voltage conversion stage, including a primary side for receiving a rectified voltage and a secondary side for generating a rectified voltage according to the rectified voltage, wherein the primary side includes a primary side switch; a switch control circuit having a startup status and a normal operation status, the switch control circuit being configured to operably provide a control signal to a control terminal of the primary side switch; a startup circuit, providing a current to the control terminal when the switch control circuit is in the startup status, to at least partially conduct the primary side switch; and a slow soft-startup circuit, wherein when the switch control circuit is in the startup status and the output voltage does not reach a predetermined voltage in a first predetermined time period, the slow soft-startup circuit reduces a total current quantity supplied to the control terminal in a second predetermined time period which is