Patents by Inventor Isabelle Claverie

Isabelle Claverie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Protection of the logic well of a component including an integrated MOS power transistor
    Patent number: 6781804
    Abstract: The present invention relates to a structure for ground connection on a component including a vertical MOS power transistor and logic components, the substrate of a first type of conductivity of the component corresponding to the drain of the MOS transistor and the logic components being formed in at least one well of the second type of conductivity and on the upper surface side of the substrate. In the logic well, a region of the first type of conductivity is formed, on which is formed a metallization, to implement, on the one hand, an ohmic contact, and on the other hand, a rectifying contact.
    Type: Grant
    Filed: July 25, 2000
    Date of Patent: August 24, 2004
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Isabelle Claverie
  • Method of manufacturing an avalanche diode with an adjustable threshold
    Patent number: 6306717
    Abstract: The present invention relates to a method of manufacturing an avalanche diode of determined threshold in a substrate of a first conductivity type with a low doping level, including the steps of diffusing in the substrate at least one first region of the first conductivity type; diffusing in the substrate a second region of the second conductivity type protruding from the first region. The opening of a mask of definition of the first region has a lateral extent smaller than the diffusion depth of the first region in the substrate, this lateral extent being chosen all the smaller as the desired avalanche threshold is high.
    Type: Grant
    Filed: March 30, 1999
    Date of Patent: October 23, 2001
    Assignee: STMicroelectronics S.A.
    Inventor: Isabelle Claverie
  • Protection of the logic well of a component including an integrated MOS power transistor
    Patent number: 6144066
    Abstract: The present invention relates to a structure for ground connection on a component including a vertical MOS power transistor and logic components, the substrate of a first type of conductivity of the component corresponding to the drain of the MOS transistor and the logic components being formed in at least one well of the second type of conductivity and on the upper surface side of the substrate. In the logic well, a region of the first type of conductivity is formed, on which is formed a metallization, to implement, on the one hand, an ohmic contact, and on the other hand, a rectifying contact.
    Type: Grant
    Filed: June 9, 1998
    Date of Patent: November 7, 2000
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Isabelle Claverie