Patents by Inventor Isako Ishikawa

Isako Ishikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Parallel pipelined instruction processing system for very long instruction word
    Patent number: 5333280
    Abstract: A parallel pipelined instruction processing system for executing a plurality of instructions in parallel without no branch delay, comprises a instruction block fetch unit for fetching an instruction block including at least one instruction field and one branch instruction field, at least one instruction execution unit receiving an instruction included in the instruction field of the instruction block held in the instruction block fetch unit and for executing the received instruction, and a branch instruction execution unit receiving a branch instruction included in the branch instruction field of the instruction block held in the instruction block fetch unit and for executing a processing for the received branch instruction.
    Type: Grant
    Filed: April 8, 1991
    Date of Patent: July 26, 1994
    Assignee: NEC Corporation
    Inventors: Isako Ishikawa, Yumiko Ushimaru