Patents by Inventor Isami Sakai

Isami Sakai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8035155
    Abstract: A nonvolatile semiconductor memory device includes a floating gate; an erasing gat; and a control gate. The floating gate is provided on a channel region of a semiconductor substrate through a first insulating layer. The erasing gate is provided on the floating gate through a second insulating layer. The control gate is provided beside the floating gate and the erasing gate through a third insulating layer. The floating gate is U-shaped.
    Type: Grant
    Filed: February 10, 2009
    Date of Patent: October 11, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Isami Sakai
  • Publication number: 20090200597
    Abstract: A nonvolatile semiconductor memory device includes a floating gate; an erasing gat; and a control gate. The floating gate is provided on a channel region of a semiconductor substrate through a first insulating layer. The erasing gate is provided on the floating gate through a second insulating layer. The control gate is provided beside the floating gate and the erasing gate through a third insulating layer. The floating gate is U-shaped.
    Type: Application
    Filed: February 10, 2009
    Publication date: August 13, 2009
    Inventor: Isami Sakai
  • Patent number: 6979856
    Abstract: A semiconductor memory device includes a first insulating film provided on a semiconductor substrate between first and second diffusion regions, a first gate electrode provided on the first insulating film, a second insulating film provided on the semiconductor substrate between the second diffusion region and a third diffusion region, and a second gate electrode provided on the second insulating film. The first and second diffusion regions, first insulating film, and first gate electrode constitute a first memory cell, while the second and third diffusion regions, second insulating film, and second gate electrode constitute a second memory cell. The first and second gate electrodes are connected in common to form a word line electrode. The first and third diffusion regions are connected to first and second read bit lines. The second diffusion region is connected to a program and erase bit line.
    Type: Grant
    Filed: August 27, 2003
    Date of Patent: December 27, 2005
    Assignee: NEC Electronics Corporation
    Inventors: Teiichiro Nishizaka, Isami Sakai, Akira Yoshino, Shinichi Kawai, Kiyokazu Ishige, Tomohiro Hamajima, Motoko Tanaka
  • Publication number: 20040071011
    Abstract: A semiconductor memory device includes a first insulating film provided on a semiconductor substrate between first and second diffusion regions, a first gate electrode provided on the first insulating film, a second insulating film provided on the semiconductor substrate between the second diffusion region and a third diffusion region, and a second gate electrode provided on the second insulating film are included, wherein the first and second diffusion regions, first insulating film, and first gate electrode constitute a first memory cell, while the second and third diffusion regions, second insulating film, and second gate electrode constitute a second memory cell. The first and second gate electrodes are connected in common to form a word line electrode. The first and third diffusion regions are connected to first and second read bit lines disposed on a layer overlying the semiconductor substrate.
    Type: Application
    Filed: August 27, 2003
    Publication date: April 15, 2004
    Applicant: NEC Electronics Corporation
    Inventors: Teiichiro Nishizaka, Isami Sakai, Akira Yoshino, Shinichi Kawai, Kiyokazu Ishige, Tomohiro Hamajima, Motoko Tanaka
  • Patent number: 6534355
    Abstract: According to the present invention, there is disclosed a 2-transistors type flash memory, wherein a memory-transistor is composed of layers of structure consisting of a floating gate and a control gate separated by a first insulating film; and, at least, a gate electrode of a select-transistor is composed of a single layer of a polysilicon film, which is formed from the same layer as the floating gate electrode of the memory-transistor and then doped to have an enhanced dopant concentration by ion implantation performed in the step of forming source-drain regions of the transistors.
    Type: Grant
    Filed: September 12, 2001
    Date of Patent: March 18, 2003
    Assignee: NEC Corporation
    Inventors: Hiroshi Ito, Isami Sakai
  • Publication number: 20020052073
    Abstract: According to the present invention, there is disclosed a 2-transistors type flash memory, wherein a memory-transistor is composed of layers of structure consisting of a floating gate and a control gate separated by a first insulating film; and, at least, a gate electrode of a select-transistor is composed of a single layer of a polysilicon film, which is formed from the same layer as the floating gate electrode of the memory-transistor and then doped to have an enhanced dopant concentration by ion implantation performed in the step of forming source-drain regions of the transistors
    Type: Application
    Filed: September 12, 2001
    Publication date: May 2, 2002
    Inventors: Hiroshi Ito, Isami Sakai
  • Patent number: 6287907
    Abstract: According to the present invention, there is disclosed a 2-transistors type flash memory, wherein a memory-transistor is composed of layers of structure consisting of a floating gate and a control gate separated by a first insulating film; and, at least, a gate electrode of a select-transistor is composed of a single layer of a polysilicon film, which is formed from the same layer as the floating gate electrode of the memory-transistor and then doped to have an enhanced dopant concentration by ion implantation performed in the step of forming source-drain regions of the transistors
    Type: Grant
    Filed: November 23, 1999
    Date of Patent: September 11, 2001
    Assignee: NEC Corporation
    Inventors: Hiroshi Ito, Isami Sakai
  • Patent number: 6051472
    Abstract: A semiconductor device of the present invention and using trench isolation includes contact holes. Spacers are formed on the shoulder portions of a device region exposed in the contact holes. To form the spacers, a silicon oxide film is formed and then etched by anisotropic etching such that the film does not fill up the contact holes. The anisotropic etching may be effected after oxidation. With this structure, it is possible to prevent junction leakage current from increasing.
    Type: Grant
    Filed: September 25, 1997
    Date of Patent: April 18, 2000
    Assignee: NEC Corporation
    Inventors: Hitoshi Abiko, Isami Sakai
  • Patent number: 5834368
    Abstract: A method for manufacturing an integrated circuit, wherein, before providing an IC composite by forming a metal film on an IC assembly which includes a semiconductor substrate and a silicon part formed along the substrate and consisting essentially of silicon, an amorphous region is formed into the silicon part. The IC composite is subjected to first primary and secondary heat treatments in a nitrogen atmosphere and then to a second heat treatment at 600.degree.-700.degree. C., 700.degree.-900.degree. C., and 700.degree.-900.degree. C. to turn the metal film on the silicon part into a metal silicide film of excellent uniformity. The assembly has a silicon dioxide portion, on which the metal film is turned during the first primary and secondary heat treatments into a metal nitride film. The second heat treatment is carried out after the removal of the metal nitride film.
    Type: Grant
    Filed: March 10, 1997
    Date of Patent: November 10, 1998
    Assignee: NEC Corporation
    Inventors: Hiroshi Kawaguchi, Isami Sakai
  • Patent number: 5696397
    Abstract: The present invention provides an input protection circuit including a first MOS FET including a source electrically connected to an input terminal and a drain and a gate both electrically connected to a grounding line, a second MOS FET including a source electrically connected to the input terminal and a drain and a gate, and a third MOS FET including a source electrically connected to a power line and a drain and a gate to both of which are electrically connected a drain and a gate of the second MOS FET. The input protection circuit shares a parasitic p-MOS transistor with an internal circuit, and hence it is no longer necessary to form a parasitic MOS transistor to be used only for an input protection circuit. Thus, the input protection circuit decreases the number of photomask using steps by one relative to a conventional protection circuit.
    Type: Grant
    Filed: April 29, 1996
    Date of Patent: December 9, 1997
    Assignee: NEC Corporation
    Inventor: Isami Sakai
  • Patent number: 5565383
    Abstract: In a method for forming silicide films on a silicon substrate being formed thereon with a gate surrounded by gate side walls and being formed therein with diffusion regions, the silicide film being formed on a predetermined region of the silicon substrate at least except for an extremely thin film on the gate side walls. The method comprises the following steps. The silicon substrate is subjected to a collimated sputtering of metal atoms with use of a meshed mask on the silicon substrate surface to deposit a metal film on an entire surface of the silicon substrate, except for an extremely thin film on the vertical walls. The deposited metal film is further subjected to a heat treatment to react the metal film with the diffusion regions to thereby selectively form a metal silicide film at least on the diffusion regions, except for an extremely thin film on the vertical walls.
    Type: Grant
    Filed: January 16, 1996
    Date of Patent: October 15, 1996
    Assignee: NEC Corporation
    Inventor: Isami Sakai
  • Patent number: 5321280
    Abstract: A composite semiconductor integrated circuit device includes logic circuit blocks of a master slice system and function blocks such as memories all of which are integrated on a single semiconductor chip. The function blocks are constituted with n lower metal wiring layers. On a portion of a surface of the chip which overlaps with the function block, a (n+1)th metal layer is not provided as signal wiring, but a (n+2)th metal wiring layer or higher layers are provided. The step coverage of the metal wiring layers provided on the chip surface portion overlapping with the function block is improved and cross-talk between signal lines can be reduced.
    Type: Grant
    Filed: September 13, 1991
    Date of Patent: June 14, 1994
    Assignee: NEC Corporation
    Inventor: Isami Sakai
  • Patent number: 5296742
    Abstract: An integrated circuit chip includes a substrate in which active circuits are formed, a lower layer of parallel conductors formed on the substrate, and one or more intermediate layers of insulating material on the lower-layer conductors, the intermediate layers having troughs corresponding to spaces where the lower-layer conductors are absent on the substrate and crests corresponding to spaces where the lower-layer conductors are present on the substrate. An upper layer of parallel conductors is formed on the insulative layers, the upper-layer conductors extending in a direction normal to the length of the lower-layer conductors. The upper-layer conductors have a minimum step coverage of 50%, and the lower-layer conductors have a ratio of a thickness thereof to a separation therebetween, which ratio is either equal to or greater than 0.45 or equal to or smaller than 0.25.
    Type: Grant
    Filed: November 21, 1991
    Date of Patent: March 22, 1994
    Assignee: NEC Corporation
    Inventor: Isami Sakai
  • Patent number: 5292674
    Abstract: Disclosed is an improved metal oxide-semiconductor field-effect transistor having two diffused regions extending apart from under one and the other edge of the gate in the opposite directions, at least one of the diffused regions being composed of a first leastdoped, short section, a second lightly-doped, short section, and a third heavily-doped, long section. Either diffused region may be used as drain. The series-connection of least and lightly-doped sections of the same longitudinal size or depth improves the current driving capability of the semiconductor device. Also, methods of making such MOSFETs are disclosed.
    Type: Grant
    Filed: November 29, 1991
    Date of Patent: March 8, 1994
    Assignee: NEC Corporation
    Inventors: Kazuhiro Okabe, Isami Sakai