Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s

Abstract: In semiconductor integrated circuit device having a DRAM including a memory cell portion formed at a first portion of a main surface of a semiconductor substrate and a peripheral circuit portion formed at a second portion of the main surface of the semiconductor substrate, bit line conductors and first level interconnect conductors in the peripheral circuit portion for connecting the memory cell portion and the peripheral circuit portion so as to exchange signals between them are constituted by conductor layers that are formed simultaneously and hence, exist at the same level. The conductor layers exist at an outside position of the memory cell portion such as in the peripheral circuit portion, and the thickness of portions of the conductor layers constituting the first level interconnect conductors of the peripheral circuit portion is greater than the thickness of portions of the conductor layers constituting the bit line conductors.

Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions. The disclosed process includes forming insulating films over wiring lines including uppermost wiring lines, the uppermost wiring lines having gaps between adjacent uppermost wiring lines. The insulating films include forming a silicon oxide film over the wiring lines and in the gaps between adjacent uppermost wiring lines, and forming a silicon nitride film over the silicon oxide film, the silicon nitride film being formed by plasma chemical vapor deposition. The silicon oxide film is formed to have a thickness of at least one-half of the gap between adjacent uppermost wiring lines, with the silicon nitride film being thicker than the silicon oxide film.

Abstract: In one embodiment, the present invention provides a method of treating a dielectric layer 24. First, the dielectric layer is heated while being subjected to an O.sub.2 plasma. After that, the dielectric layer is heated while being subject to an ozone environment. This method can be useful in forming a capacitor 12 dielectric 24. In turn, the capacitor could be used in a DRAM memory device.

Abstract: In semiconductor integrated circuit device having a DRAM including a memory cell portion formed at a first portion of a main surface of a semiconductor substrate and a peripheral circuit portion formed at a second portion of the main surface of the semiconductor substrate, bit line conductors and first level interconnect conductors in the peripheral circuit portion for connecting the memory cell portion and the peripheral circuit portion so as to exchange signals between them are constituted by conductor layers that are formed simultaneously and hence, exist at the same level. The conductor layers exist at an outside position of the memory cell portion such as in the peripheral circuit portion, and the thickness of portions of the conductor layers constituting the first level interconnect conductors of the peripheral circuit portion is greater than the thickness of portions of the conductor layers constituting the bit line conductors.

Abstract: The semiconductor device is formed according to the following steps. A TiN film 71 and a W film 72 are deposited on a silicon oxide film 64 including the inside of a via-hole 66 by the CVD method and thereafter, the W film 72 and TiN film 71 on the silicon oxide film 64 are etched back to leave only the inside of the via-hole 66 and form a plug 73. Then, a TiN film 74, Al-alloy film 75, and Ti film 76 are deposited on the silicon oxide film 64 including the surface of the plug 73 by the sputtering method and thereafter, the Ti film 76, Al-alloy film 75, and TiN film 74 are patterned to form second-layer wirings 77 and 78.

Abstract: In a process for manufacturing a semiconductor integrated circuit device having a MISFET, in order that a shallow junction between the source/drain of the MISFET and a semiconductor substrate may be realized by reducing the number of heat treatment steps, all conductive films to be deposited on the semiconductor substrate are deposited at a temperature of 500.degree. C. or lower at a step after the MISFET has been formed. Moreover, all insulating films to be deposited over the semiconductor substrate are deposited at a temperature of 500.degree. C. or lower at a step after the MISFET has been formed.

Abstract: A self-aligned multiple crown storage cell structure 10 for use in a semiconductor memory device and method of formation that provide a storage capacitor with increased capacitance. A double crown storage cell structure embodiment 10 can be formed by patterning a contact via 18 into a planarized base layer that can include an insulating layer 12, an etch stop layer 14, and a hard mask layer 16, depositing a first conductive layer 20, etching the first conductive layer 20, etching the hard mask layer 16, depositing a second conductive layer 24 onto the conductive material-coated patterned via 18 and the etch stop layer 14, depositing a sacrificial (oxide) layer 26 onto the second conductive layer 24, etching the sacrificial layer 26, depositing a third conductive layer 28, and etching conductive material and the remaining sacrificial layer 26. The last several steps can be repeated to form a storage cell structure 10 with three or more crowns.

Abstract: A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, is disclosed. In a first aspect, the impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry.

Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s

Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s

Abstract: A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, is disclosed. In a first aspect, the impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry.

Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s

Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s

Abstract: A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, is disclosed. The impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. The Y-select signal line overlaps the lower electrode layer of the capacitor element. A potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected, is formed by diffusion of an impurity for a channel stopper region. The dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it. The capacitor dielectric film is a silicon nitride film having a silicon oxide layer thereon, the silicon oxide layer being formed by oxidizing a surface layer of the silicon nitride under high pressure.

Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s

Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s

Abstract: A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, such as a DRAM, is disclosed. In a first aspect of the present invention, the impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. In a second aspect, the Y-select signal line overlaps the lower electrode layer of the capacitor element. In a third aspect, a potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected, is formed by diffusion of an impurity for a channel stopper region. In a fourth aspect, the dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it.

Abstract: In a semiconductor integrated circuit device having a fine multilayer interconnection structure, a wiring material such as tungsten is formed on a predetermined part of the interior of a wiring layer-forming groove formed in a flat inter-layer insulating film by selective deposition. The flat inter-layer insulating film has a laminate structure of two or more insulating films different in etching speed, and a (first) insulating film, underlying a (second) insulating film in which the wiring layer-forming groove of the inter-layer insulating film is formed, serves as an etching stopper to make the depth of the wiring layer-forming groove constant when forming the groove from etching. Consequently, the depth of the wiring layer-forming groove can be defined accurately by the thickness of a (second) insulating film formed by deposition, and the film thickness between wiring layers can be accurately defined by the thickness of an insulating film formed by deposition.

Abstract: A compact sensing device is provided which the tension applied to the sensing member is substantially uniform and free of thermally changing. Either the sensing member itself or a clamping member disposed around the device or both, are made of a precipitation hardenable metal which will contract during a heat treatment. If the sensing member is thermally contracted a uniform radial tension will result, and if the clamping member is contracted a uniform clamping force applied to the device for tensioning the diaphragm will be provided without the necessity of clamping bolts.