Patents by Inventor Isamu Hayashi
Isamu Hayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10018539Abstract: A protein retrieval treatment system used for activating proteins contained in a deparaffinized tissue section obtained by removing paraffin from a formalin-fixed paraffin embedded tissue section. The protein retrieval treatment system includes: a dispensing unit for dispensing a retrieval treatment solution over a dispensing area including a measurement area on the deparaffinized tissue section; and a moist-heat treatment unit for heating, in a saturated water vapor, the deparaffinized tissue section with the dispensing area covered with the retrieval treatment solution.Type: GrantFiled: December 22, 2015Date of Patent: July 10, 2018Assignees: SHIMADZU CORPORATION, SHIZUOKA PREFECTUREInventors: Yutaka Aoki, Yukari Umino, Taka-Aki Sato, Isamu Hayashi, Keiichi Hatakeyama, Shun-ichiro Ogura
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Patent number: 9921638Abstract: The data processing system has: a plurality of hardware resources each having at least one standby mode; a control part for controlling execution of a task achieved by using, of the plurality of hardware resources, predetermined ones, and a working status of each hardware resource; and a power-source part for controlling supply of a power source to each hardware resource. The control part performs the scheduling of a scheduled execution time of the task based on information for determining a timing of executing the task, and calculates a standby time of the hardware resource based on a result of the scheduling. The control part compares the standby time with a break-even time depending on the standby mode, thereby deciding whether or not to cause each hardware resource to transition to the standby mode.Type: GrantFiled: September 29, 2014Date of Patent: March 20, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Masaru Haraguchi, Isamu Hayashi, Hiroyuki Kawai, Hideyuki Noda
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Publication number: 20180061153Abstract: An information providing system of a vehicle includes a portable terminal that captures a picture of an inquiry target of an apparatus and equipment of the vehicle and transmits the captured picture, a recognition unit that recognizes the inquiry target indicated by the picture transmitted from the portable terminal, a processing unit that has a plurality of pieces of explanation information for explanation of the apparatus and the equipment, and selects and transmits the explanation information corresponding to the inquiry target recognized by the recognition unit, and a display unit that is provided in the vehicle to display the explanation information transmitted from the processing unit.Type: ApplicationFiled: August 30, 2017Publication date: March 1, 2018Applicant: MITSUBISHI JIDOSHA KOGYO KABUSHIKI KAISHAInventors: Shien HO, Isamu HAYASHI
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Patent number: 9620214Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.Type: GrantFiled: April 20, 2015Date of Patent: April 11, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Naoya Watanabe, Isamu Hayashi, Teruhiko Amano, Fukashi Morishita, Kenji Yoshinaga, Mihoko Akiyama, Shinya Miyazaki, Masakazu Ishibashi, Katsumi Dosaka
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Patent number: 9360922Abstract: In order to perform easily power cutoff of a device configuring a data processing system and to improve the power reduction effect at standby, the data processing system is configured with a microcontroller, a memory IC including a nonvolatile RAM array, and a power supply unit capable of controlling the power supply to the microcontroller and the memory IC, separately. When a control signal to control read and write of data to the nonvolatile RAM array is at a high level, the memory IC is enabled read and write of data to the nonvolatile RAM array. When the control signal is at a low level, the memory IC is disenabled read and write of data to the nonvolatile RAM array. The microcontroller sets the control signal at a low level, when the memory IC is shifted to a standby state by the power supply unit.Type: GrantFiled: September 29, 2014Date of Patent: June 7, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Masaru Haraguchi, Isamu Hayashi, Hiroyuki Kawai
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Publication number: 20160153872Abstract: A protein retrieval treatment system used for activating proteins contained in a deparaffinized tissue section obtained by removing paraffin from a formalin-fixed paraffinembedded tissue section. The protein retrieval treatment system includes: a dispensing unit for dispensing a retrieval treatment solution over a dispensing area including a measurement area on the deparaffinized tissue section; and a moist-heat treatment unit for heating, in a saturated water vapor, the deparaffinized tissue section with the dispensing area covered with the retrieval treatment solution.Type: ApplicationFiled: December 22, 2015Publication date: June 2, 2016Applicants: SHIMADZU CORPORATION, SHIZUOKA PREFECTUREInventors: Yutaka AOKI, Yukari UMINO, Taka-Aki SATO, Isamu HAYASHI, Keiichi HATAKEYAMA, Shun-ichiro OGURA
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Publication number: 20150228341Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.Type: ApplicationFiled: April 20, 2015Publication date: August 13, 2015Inventors: Naoya WATANABE, Isamu HAYASHI, Teruhiko AMANO, Fukashi MORISHITA, Kenji YOSHINAGA, Mihoko AKIYAMA, Shinya MIYAZAKI, Masakazu ISHIBASHI, Katsumi DOSAKA
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Patent number: 9042148Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.Type: GrantFiled: January 9, 2014Date of Patent: May 26, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Naoya Watanabe, Isamu Hayashi, Teruhiko Amano, Fukashi Morishita, Kenji Yoshinaga, Mihoko Akiyama, Shinya Miyazaki, Masakazu Ishibashi, Katsumi Dosaka
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Publication number: 20150095672Abstract: The data processing system has: a plurality of hardware resources each having at least one standby mode; a control part for controlling execution of a task achieved by using, of the plurality of hardware resources, predetermined ones, and a working status of each hardware resource; and a power-source part for controlling supply of a power source to each hardware resource. The control part performs the scheduling of a scheduled execution time of the task based on information for determining a timing of executing the task, and calculates a standby time of the hardware resource based on a result of the scheduling. The control part compares the standby time with a break-even time depending on the standby mode, thereby deciding whether or not to cause each hardware resource to transition to the standby mode.Type: ApplicationFiled: September 29, 2014Publication date: April 2, 2015Inventors: Masaru HARAGUCHI, Isamu Hayashi, Hiroyuki Kawai, Hideyuki Noda
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Publication number: 20150095684Abstract: In order to perform easily power cutoff of a device configuring a data processing system and to improve the power reduction effect at standby, the data processing system is configured with a microcontroller, a memory IC including a nonvolatile RAM array, and a power supply unit capable of controlling the power supply to the microcontroller and the memory IC, separately. When a control signal to control read and write of data to the nonvolatile RAM array is at a high level, the memory IC is enabled read and write of data to the nonvolatile RAM array. When the control signal is at a low level, the memory IC is disenabled read and write of data to the nonvolatile RAM array. The microcontroller sets the control signal at a low level, when the memory IC is shifted to a standby state by the power supply unit.Type: ApplicationFiled: September 29, 2014Publication date: April 2, 2015Inventors: Masaru HARAGUCHI, Isamu HAYASHI, Hiroyuki KAWAI
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Publication number: 20140220624Abstract: A protein retrieval treatment system used for activating proteins contained in a deparaffinized tissue section obtained by removing paraffin from a formalin-fixed paraffin-embedded tissue section. The protein retrieval treatment system includes: a dispensing unit for dispensing a retrieval treatment solution over a dispensing area including a measurement area on the deparaffinized tissue section; and a moist-heat treatment unit for heating, in a saturated water vapor, the deparaffinized tissue section with the dispensing area covered with the retrieval treatment solution.Type: ApplicationFiled: April 25, 2012Publication date: August 7, 2014Applicants: SHIZUOKA PREFECTURE, SHIMADZU CORPORATIONInventors: Yutaka Aoki, Yukari Umino, Taka-Aki Sato, Isamu Hayashi, Keiichi Hatakeyama, Shun-ichiro Ogura
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Publication number: 20140126264Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.Type: ApplicationFiled: January 9, 2014Publication date: May 8, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Naoya WATANABE, Isamu Hayashi, Teruhiko Amano, Fukashi Morishita, Kenji Yoshinaga, Mihoko Akiyama, Shinya Miyazaki, Masakazu Ishibashi, Katsumi Dosaka
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Patent number: 8638583Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.Type: GrantFiled: September 15, 2012Date of Patent: January 28, 2014Assignee: Renesas Electronics CorporationInventors: Naoya Watanabe, Isamu Hayashi, Teruhiko Amano, Fukashi Morishita, Kenji Yoshinaga, Mihoko Akiyama, Shinya Miyazaki, Masakazu Ishibashi, Katsumi Dosaka
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Patent number: 8487708Abstract: An object is to provide a method for preventing the occurrence of variations in time resolution by providing a calibration process to a TDC at the time of start up and further preventing the increase in circuit scale by reducing the redundancy of delay elements. A calibration of a multiphase oscillator TDC and a vernier TDC is carried out at the time of power-on. In the calibration, a timing input to be input to the vernier TDC is selected from output signals of DCCO based on a reference clock. Also, data is defined as an output signal which is adjacent to the output signal of DCCO mentioned above and proceeds in phase, and the delay therebetween is derived. By repeating it to all of the output signals, the one cycle of the output signal of DCCO is derived.Type: GrantFiled: October 31, 2011Date of Patent: July 16, 2013Assignee: Renesas Electronics CorporationInventor: Isamu Hayashi
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Publication number: 20130010513Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.Type: ApplicationFiled: September 15, 2012Publication date: January 10, 2013Inventors: Naoya WATANABE, Isamu Hayashi, Teruhiko Amano, Fukashi Morishita, Kenji Yoshinaga, Mihoko Akiyama, Shinya Miyazaki, Masakazu Ishibashi, Katsumi Dosaka
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Patent number: 8310852Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.Type: GrantFiled: March 13, 2012Date of Patent: November 13, 2012Assignee: Renesas Electronics CorporationInventors: Naoya Watanabe, Isamu Hayashi, Teruhiko Amano, Fukashi Morishita, Kenji Yoshinaga, Mihoko Akiyama, Shinya Miyazaki, Masakazu Ishibashi, Katsumi Dosaka
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Publication number: 20120170344Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.Type: ApplicationFiled: March 13, 2012Publication date: July 5, 2012Applicant: Renesas Electronics CorporationInventors: Naoya WATANABE, Isamu HAYASHI, Teruhiko AMANO, Fukashi MORISHITA, Kenji YOSHINAGA, Mihoko AKIYAMA, Shinya MIYAZAKI, Masakazu ISHIBASHI, Katsumi DOSAKA
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Publication number: 20120112841Abstract: An object is to provide a method for preventing the occurrence of variations in time resolution by providing a calibration process to a TDC at the time of start up and further preventing the increase in circuit scale by reducing the redundancy of delay elements. A calibration of a multiphase oscillator TDC and a vernier TDC is carried out at the time of power-on. In the calibration, a timing input to be input to the vernier TDC is selected from output signals of DCCO based on a reference clock. Also, data is defined as an output signal which is adjacent to the output signal of DCCO mentioned above and proceeds in phase, and the delay therebetween is derived. By repeating it to all of the output signals, the one cycle of the output signal of DCCO is derived.Type: ApplicationFiled: October 31, 2011Publication date: May 10, 2012Inventor: Isamu Hayashi
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Patent number: 8164934Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.Type: GrantFiled: March 9, 2010Date of Patent: April 24, 2012Assignee: Renesas Electronics CorporationInventors: Naoya Watanabe, Isamu Hayashi, Teruhiko Amano, Fukashi Morishita, Kenji Yoshinaga, Mihoko Akiyama, Shinya Miyazaki, Masakazu Ishibashi, Katsumi Dosaka
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Publication number: 20100165691Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.Type: ApplicationFiled: March 9, 2010Publication date: July 1, 2010Applicant: Renesas Technology Corp.Inventors: Naoya WATANABE, Isamu HAYASHI, Teruhiko AMANO, Fukashi MORISHITA, Kenji YOSHINAGA, Mihoko AKIYAMA, Shinya MIYAZAKI, Masakazu ISHIBASHI, Katsumi DOSAKA