Abstract: A 3D image display apparatus comprises a transmission-reception device and a control signal output device. The transmission-reception device receives a video data including a plurality of image informations which is base data of 3D images from a 3D image playback apparatus through a transmission cable and thereby generates an image signal. The control signal output device transmits a control signal for controlling light penetration states of penetration units for right and left eyes to shutter glasses. The transmission-reception device receives the video data from the 3D image playback apparatus through the transmission cable and thereby generates the image signal and a synchronizing signal. The synchronizing signal indicates which of the plurality of image informations is included in the image signal currently outputted. The control signal output device generates the control signal based on the synchronizing signal.

Abstract: An authentication processing apparatus includes an authentication unit, having a circuit that performs authentication phases included in processing for authenticating an external device. A command holding unit holds a first command that indicates whether or not each of the authentication phases is performed by the authentication unit. An authentication controller causes the authentication unit to perform an authentication phase that is indicated, by the first command, to be performed by the authentication unit. A CPU performs software processing of an authentication phase that is indicated, by the first command, not to be performed by the authentication unit.

Abstract: A video output apparatus includes a video output unit which outputs a video signal while switching the format of the video signal between a first format and a second format for expressing color differently. The video output apparatus also includes a mute signal generation unit which generates, as a muting video signal, a specialized video signal expressing a color in which the difference between the color displayed when the specialized video signal is interpreted in its own format and the color displayed when the specialized video signal is interpreted in a different format is a minimum. The video output apparatus further includes a selection unit, which selects one of the video signal outputted by said video output unit and the mute signal generated by said mute signal generation unit and outputs the selected signal, and a control unit, which causes the selection unit to select the mute signal in a period including the switch performed by the video output unit.

Abstract: An audio-video output apparatus of the present invention outputs at least one of audio data and video data to a receiving apparatus using High-Definition Multimedia Interface (HDMI) communications. The audio-video output apparatus includes a list holding unit, an authenticating unit, a list acquiring unit, an updating unit, and an apparatus verifying unit. The list holding unit holds an unauthorized apparatus list which shows information about unauthorized apparatuses. The authenticating unit performs first apparatus authentication to verify whether or not the receiving apparatus is an authorized apparatus using the unauthorized apparatus list held by the list holding unit, and performs second apparatus authentication at regular intervals to verify the receiving apparatus is an authorized apparatus. The list acquiring unit acquires another unauthorized apparatus list.

Abstract: In transmission of video signals of a plurality of channels using a digital interface in conformity with the high definition multimedia interface (HDMI) standard, a transmission minimized differential signaling (TMDS) mixing circuit and a TMDS separation circuit are provided, to perform time-division transmission of TMDS data of the video signals of the plurality of channels at a frequency higher than the transmission rate of the video signals. Video signals of a plurality of channels are therefore transmitted via an inexpensive type A connector and cable.

Abstract: In transmission of video signals of a plurality of channels using a digital interface in conformity with the high definition multimedia interface (HDMI) standard, a transmission minimized differential signaling (TMDS) mixing circuit and a TMDS separation circuit are provided, to perform time-division transmission of TMDS data of the video signals of the plurality of channels at a frequency higher than the transmission rate of the video signals. Video signals of a plurality of channels are therefore transmitted via an inexpensive type A connector and cable.

Abstract: An audio-video output apparatus of the present invention outputs at least one of audio data and video data to a receiving apparatus using High-Definition Multimedia Interface (HDMI) communications. The audio-video output apparatus includes a list holding unit, an authenticating unit, a list acquiring unit, an updating unit, and an apparatus verifying unit. The list holding unit holds an unauthorized apparatus list which shows information about unauthorized apparatuses. The authenticating unit performs first apparatus authentication to verify whether or not the receiving apparatus is an authorized apparatus using the unauthorized apparatus list held by the list holding unit, and performs second apparatus authentication at regular intervals to verify the receiving apparatus is an authorized apparatus. The list acquiring unit acquires another unauthorized apparatus list.

Abstract: The authentication processing apparatus according to the present invention includes: an authentication unit having a circuit that performs authentication phases included in processing for authenticating an external device; a command holding unit which holds a first command that indicates whether or not to perform each of the authentication phases; and an authentication control unit which causes the authentication unit to perform an authentication phase that is indicated by the first command as an authentication phase which is to be performed.

Abstract: A video output apparatus including: a video output unit which outputs a video signal while switching the format of the video signal between a first format and a second format for expressing color differently; a mute signal generation unit which generates, as a muting video signal, a specialized video signal expressing a color in which the difference between the color displayed when the specialized video signal is interpreted in its own format and the color displayed when the specialized video signal is interpreted in a different format is a minimum; a selection unit which selects one of the video signal outputted by said video output unit and the mute signal generated by said mute signal generation unit, and outputs the selected signal; and a control unit which causes the selection unit to select the mute signal in a period including the switch performed by the video output unit.

Abstract: In a system in which a CPU contained LSI and an external CPU share a bus, when the external CPU accesses a device to be controlled which is connected to a bus, the access to a device mounted on the common bus is not prevented in the CPU contained LSI. A CPU contained LSI includes a CPUa, common address/data buses 111 and 112 connected to the CPUa, CPUb address/data buses 211 and 212 connected to a CPUb, and a bus adjusting circuit 105 disposed between the common address/data buses and the CPUb address/data buses to exclusively control accesses from the CPUa and the CPUb to a device connected to the common address/data buses and connect the CPUb adress/data buses to the common address/data buses only when the CPUb is permitted to access the device connected to the common address/data buses.

Abstract: In order to reduce load placed on a CPU (central processing unit) in providing SBP-2 (serial bus protocol 2) initiator capability, provided are a sequence control circuit activated by the CPU for controlling a command issue sequence, a packet processing circuit for assembling operation request blocks (ORB) into a transmission packet and extracting a status from a received packet; buffer for storing a command ORB provided by the CPU; a buffer for storing a management ORB provided by the CPU; a buffer for storing a status received for an issued management ORB and providing the status to the CPU; and a buffer for command for storing a status received for an issued command ORB and providing the status to the CPU.

Abstract: On a commercial product mounting substrate 100, an IEEE1394 controller LSI 101 and CPU 103 which controls the IEEE1394 controller LSI 101 are mounted. A built-in PHY 102 having two ports is mounted on the IEEE1394 controller LSI 101. In addition, an external PHY 105 having three ports is also mounted on the commercial product mounting substrate 100. One port of the built-in PHY 102 and one port of the external PHY 105 are connected with each other by wiring on the commercial product mounting substrate 100. Remaining one port of the built-in PHY 102 and remaining two ports of the external PHY 105 are connected to connectors A, B and C, respectively, by wiring on the commercial product mounting substrate 100, and as a result, the number of connectors of a commercial product becomes three.

Abstract: A data transfer device which set an address of page as transfer destination and transfer data to the page. In the data transfer device to which the present invention is applied, an address and page length of a page are acquired on the basis of an address of a page table specified by a read command. Then, transfer information including the address of transfer source, transfer data length and address of transfer destination of data is set according to page element of page as transfer destination page. Then, it is judged whether the transfer destination page and other page form a continuous area. And if it is judged that the continuous area is formed, transfer information will be changed. Data transfer is effected on the basis of changed transfer information. That reduces the need to set the other area at the transfer destination and thus the transfer efficiency improves.

Abstract: A reception buffer, a transmission buffer, a transmission-reception buffer, a reception filter, a transmission filter and a packet processor are provided. If a response packet paired with a request packet has been received during a data exchange operation, then the reception filter stores the response packet received on the transmission-reception buffer and informs the packet processor of response detected. Alternatively, if a packet that has nothing to do with the current data exchange operation has been received, then the reception filter stores the received packet on the reception buffer and issues a suspension instruction to the packet processor. And when a transaction being carried out at the time of reception is completed, the packet processor suspends the data exchange. In this manner, the overheads involved with firmware processing by a central processing unit can be reduced and data can be exchanged at higher speeds.

Abstract: In a system in which a CPU contained LSI and an external CPU share a bus, when the external CPU accesses a device to be controlled which is connected to a bus, the access to a device mounted on the common bus is not prevented in the CPU contained LSI.

Abstract: A reception buffer, a transmission buffer, a transmission-reception buffer, a reception filter, a transmission filter and a packet processor are provided. If a response packet paired with a request packet has been received during a data exchange operation, then the reception filter stores the response packet received on the transmission-reception buffer and informs the packet processor of response detected. Alternatively, if a packet that has nothing to do with the current data exchange operation has been received, then the reception filter stores the received packet on the reception buffer and issues a suspension instruction to the packet processor. And when a transaction being carried out at the time of reception is completed, the packet processor suspends the data exchange. In this manner, the overheads involved with firmware processing by a central processing unit can be reduced and data can be exchanged at higher speeds.

Abstract: Reception buffer, transmission buffer, transmission-reception buffer, reception filter and transmission filter are provided. The reception filter determines where a received packet should be stored based on the contents of the received packet. Specifically, in executing a READ command, a response packet, which is returned in response to a data transmission packet, is detected by the reception filter. Received packets of the other types are stored on the reception buffer. In executing a WRITE command, a data request packet is transmitted from the transmission buffer. A data reception packet responding to the data request packet is stored by the reception filter on the transmission-reception buffer. Received packets of the other types are stored on the reception buffer. The capacity of the transmission-reception buffer is twice as large as the size of a maximum transferable packet. Thus, overhead can be reduced and yet data can be transferred at higher speeds.

Abstract: In order to reduce load placed on a CPU (central processing unit) in providing SBP-2 (serial bus protocol 2) initiator capability, provided are a sequence control circuit activated by the CPU for controlling a command issue sequence, a packet processing circuit for assembling operation request blocks (ORB) into a transmission packet and extracting a status from a received packet; buffer for storing a command ORB provided by the CPU; a buffer for storing a management ORB provided by the CPU; a buffer for storing a status received for an issued management ORB and providing the status to the CPU; and a buffer for command for storing a status received for an issued command ORB and providing the status to the CPU.

Abstract: A data transfer device which set an address of page as transfer destination and transfer data to the page. In the data transfer device to which the present invention is applied, an address and page length of a page are acquired on the basis of an address of a page table specified by a read command. Then, transfer information including the address of transfer source, transfer data length and address of transfer destination of data is set according to page element of page as transfer destination page. Then, it is judged whether the transfer destination page and other page form a continuous area. And if it is judged that the continuous area is formed, transfer information will be changed. Data transfer is effected on the basis of changed transfer information. That reduces the need to set the other area at the transfer destination and thus the transfer efficiency improves.