Patents by Inventor Isamu Kuno

Isamu Kuno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7557428
    Abstract: A semiconductor integrated circuit that includes a circuit element with a reduced parasitic capacitance and has a short start-up time. A well of the different type of conduction from that of the substrate is formed in the area of the surface of the semiconductor substrate under the circuit element. A constant voltage, which biases the junction between the well and the semiconductor substrate in a reverse direction, is applied to the well through a resistor having a higher impedance compared with the impedance of the capacitance of the reverse-biased junction between the well and the substrate at the frequency of the signal applied to the circuit element.
    Type: Grant
    Filed: January 12, 2006
    Date of Patent: July 7, 2009
    Assignee: Kawasaki Microelectronics, Inc.
    Inventors: Hiroyasu Kunitomo, Tomoaki Nimura, Isamu Kuno, Ryuji Ariyoshi
  • Patent number: 7087974
    Abstract: An anti-fuse is manufactured by forming an isolation region including an insulating material layer buried in a surface of a device formation region on a surface of a semiconductor substrate, and by forming diffusion regions at both sides of the isolation region, then by contacting electrodes to the respective diffusion regions. The anti-fuse is initially in a non-conductive state, and is programmed to be in a permanently conductive state by a simple writing circuit.
    Type: Grant
    Filed: February 9, 2004
    Date of Patent: August 8, 2006
    Assignee: Kawasaki Microelectronics Inc.
    Inventors: Isamu Kuno, Tomoharu Katagiri
  • Publication number: 20060157822
    Abstract: A semiconductor integrated circuit that includes a circuit element with a reduced parasitic capacitance and has a short start-up time. A well of the different type of conduction from that of the substrate is formed in the area of the surface of the semiconductor substrate under the circuit element. A constant voltage, which biases the junction between the well and the semiconductor substrate in a reverse direction, is applied to the well through a resistor having a higher impedance compared with the impedance of the capacitance of the reverse-biased junction between the well and the substrate at the frequency of the signal applied to the circuit element.
    Type: Application
    Filed: January 12, 2006
    Publication date: July 20, 2006
    Applicant: Kawasaki Microelectronics, Inc.
    Inventors: Hiroyasu Kunitomo, Tomoaki Nimura, Isamu Kuno, Ryuji Ariyoshi
  • Publication number: 20050224910
    Abstract: Exemplary semiconductor integrated circuits are disclosed that include polysilicon fuses that can be programmed by supplying programming currents. The fuse is formed of a polysilicon film having a sheet resistance of 1.7 to 6 k?/sq. As a result, the polysilicon fuse has a high resistance and can be programmed with low current. Accordingly, the fuse can be programmed with a high yield even when the programming current is supplied through a wire having a high resistance.
    Type: Application
    Filed: March 28, 2005
    Publication date: October 13, 2005
    Applicant: KAWASAKI MICROELECTRONICS INC.
    Inventors: Isamu Kuno, Hideaki Tokita
  • Publication number: 20040159907
    Abstract: An anti-fuse is manufactured by forming an isolation region including an insulating material layer buried in a surface of a device formation region on a surface of a semiconductor substrate, and by forming diffusion regions at both sides of the isolation region, then by contacting electrodes to the respective diffusion regions. The anti-fuse is initially in a non-conductive state, and is programmed to be in a permanently conductive state by a simple writing circuit.
    Type: Application
    Filed: February 9, 2004
    Publication date: August 19, 2004
    Applicant: KAWASAKI MICROELECTRONICS, INC.
    Inventors: Isamu Kuno, Tomoharu Katagiri
  • Patent number: 6710415
    Abstract: A semiconductor integrated contains a first MOS transistor of a first conductivity type formed on a surface of a semiconductor substrate, and a second MOS transistor of the first conductivity type having a drain-source breakdown voltage lower than that of the first MOS transistor. The second MOS transistor is used as an anti-fuse, which can be changed to a conductive state with a low writing voltage that does not damage the first MOS transistor. The second MOS transistor is fabricated such that a concentration of a second conductivity type impurity in at least a portion of the channel region adjacent to the drain region is higher than that in a corresponding portion of the first MOS transistor.
    Type: Grant
    Filed: June 16, 2003
    Date of Patent: March 23, 2004
    Assignee: Kawasaki Microelectronics, Inc.
    Inventors: Ryuji Ariyoshi, Isamu Kuno, Takahito Fukushima, Junji Aoike
  • Publication number: 20030214014
    Abstract: A semiconductor integrated contains a first MOS transistor of a first conductivity type formed on a surface of a semiconductor substrate, and a second MOS transistor of the first conductivity type having a drain-source breakdown voltage lower than that of the first MOS transistor. The second MOS transistor is used as an anti-fuse, which can be changed to a conductive state with a low writing voltage that does not damage the first MOS transistor. The second MOS transistor is fabricated such that a concentration of a second conductivity type impurity in at least a portion of the channel region adjacent to the drain region is higher than that in a corresponding portion of the first MOS transistor.
    Type: Application
    Filed: June 16, 2003
    Publication date: November 20, 2003
    Applicant: KAWASAKI MICROELECTRONICS, INC.
    Inventors: Ryuji Ariyoshi, Isamu Kuno, Takahito Fukushima, Junji Aoike
  • Patent number: 6608355
    Abstract: A semiconductor integrated contains a first MOS transistor of a first conductivity type formed on a surface of a semiconductor substrate, and a second MOS transistor of the first conductivity type having a drain-source breakdown voltage lower than that of the first MOS transistor. The second MOS transistor is used as an anti-fuse, which can be changed to a conductive state with a low writing voltage that does not damage the first MOS transistor. The second MOS transistor is fabricated such that a concentration of a second conductivity type impurity in at least a portion of the channel region adjacent to the drain region is higher than that in a corresponding portion of the first MOS transistor.
    Type: Grant
    Filed: February 19, 2002
    Date of Patent: August 19, 2003
    Assignee: Kawasaki Microelectronics, Ltd.
    Inventors: Ryuji Ariyoshi, Isamu Kuno, Takahito Fukushima, Junji Aoike
  • Publication number: 20020117724
    Abstract: A semiconductor integrated contains a first MOS transistor of a first conductivity type formed on a surface of a semiconductor substrate, and a second MOS transistor of the first conductivity type having a drain-source breakdown voltage lower than that of the first MOS transistor. The second MOS transistor is used as an anti-fuse, which can be changed to a conductive state with a low writing voltage that does not damage the first MOS transistor. The second MOS transistor is fabricated such that a concentration of a second conductivity type impurity in at least a portion of the channel region adjacent to the drain region is higher than that in a corresponding portion of the first MOS transistor.
    Type: Application
    Filed: February 19, 2002
    Publication date: August 29, 2002
    Applicant: KAWASAKI MICROELECTRONICS INC.
    Inventors: Ryuji Ariyoshi, Isamu Kuno, Takahito Fukushima, Junji Aoike