Patents by Inventor Isamu Mashima

Isamu Mashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for redundant memory configuration in voltage island
    Patent number: 7859934
    Abstract: A method and apparatus to configure redundant memory elements in a system on a chip (SoC) having discrete voltage domains (islands). A plurality of memories are provided for each voltage island, each containing redundancy elements or having the capability to access redundant memory elements in a neighboring voltage domain; a fuse cell stores configuration information for controlling the switching of memory elements of the plurality of memories; a shift register receives and retains configuration information on a memory array from the fuse cell corresponding to each memory; and a control circuit directs operation of the shift register. The shift register includes a shift portion for receiving the data of the configuration information and transferring the data to another shift register, and a latch portion for retaining the data inputted to the shift portion.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: December 28, 2010
    Assignee: International Business Machines Corporation
    Inventors: Masayoshi Taniguchi, Isamu Mashima, Jun Usami
  • METHOD AND APPARATUS FOR REDUNDANT MEMORY CONFIGURATION IN VOLTAGE ISLAND
    Publication number: 20090097335
    Abstract: A method and apparatus to configure redundant memory elements in a system on a chip (SoC) having discrete voltage domains (islands). A plurality of memories are provided for each voltage island, each containing redundancy elements or having the capability to access redundant memory elements in a neighboring voltage domain; a fuse cell stores configuration information for controlling the switching of memory elements of the plurality of memories; a shift register receives and retains configuration information on a memory array from the fuse cell corresponding to each memory; and a control circuit directs operation of the shift register. The shift register includes a shift portion for receiving the data of the configuration information and transferring the data to another shift register, and a latch portion for retaining the data inputted to the shift portion.
    Type: Application
    Filed: December 9, 2008
    Publication date: April 16, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: MASAYOSHI TANIGUCHI, ISAMU MASHIMA, JUN USAMI
  • Method and apparatus for redundant memory configuration in voltage island
    Patent number: 7477564
    Abstract: A method and apparatus to configure redundant memory elements in a system on a chip (SoC) having discrete voltage domains (islands). A plurality of memories are provided for each voltage island, each containing redundancy elements or having the capability to access redundant memory elements in a neighboring voltage domain; a fuse cell stores configuration information for controlling the switching of memory elements of the plurality of memories; a shift register receives and retains configuration information on a memory array from the fuse cell corresponding to each memory; and a control circuit directs operation of the shift register. The shift register includes a shift portion for receiving the data of the configuration information and transferring the data to another shift register, and a latch portion for retaining the data inputted to the shift portion.
    Type: Grant
    Filed: December 20, 2005
    Date of Patent: January 13, 2009
    Assignee: International Business Machines Corporation
    Inventors: Masayoshi Taniguchi, Isamu Mashima, Jun Usami
  • METHOD AND APPARATUS FOR REDUNDANT MEMORY CONFIGURATION IN VOLTAGE ISLAND
    Publication number: 20070109882
    Abstract: A method and apparatus to configure redundant memory elements in a system on a chip (SoC) having discrete voltage domains (islands). A plurality of memories are provided for each voltage island, each containing redundancy elements or having the capability to access redundant memory elements in a neighboring voltage domain; a fuse cell stores configuration information for controlling the switching of memory elements of the plurality of memories; a shift register receives and retains configuration information on a memory array from the fuse cell corresponding to each memory; and a control circuit directs operation of the shift register. The shift register includes a shift portion for receiving the data of the configuration information and transferring the data to another shift register, and a latch portion for retaining the data inputted to the shift portion.
    Type: Application
    Filed: December 20, 2005
    Publication date: May 17, 2007
    Inventors: Masayoshi Taniguchi, Isamu Mashima, Jun Usami