Abstract: A multi-input logic circuit which operates in a push-pull manner is composed of first and second logic sections. The first logic section is coupled between an output terminal and a reference voltage source and composed of a plurality of enhancement field effect transistors receiving a plurality of first input signals. The second logic section is coupled between the output terminal and a power source and composed of a plurality of depletion field effect transistors receiving a plurality of second input signals complementary to the first logic signals.

Abstract: An insulated-gate field effect transistor for high speed operation is disclosed in which the internal resistance of the gate electrode is reduced and the stray gate capacitance is maintained at a low value. In one embodiment, the reduction of the internal resistance of the gate electrode is effected by leading the gate electrode out of the transistor structure across, but above, the drain or source region in a bridge-like fashion. According to the method disclosed herein, the degree of integration of such IC devices is enhanced, and the lengths of the gate insulator film and the channel may be precisely defined.