Abstract: A semiconductor integrated circuit includes a plurality of processing circuits including a sample and hold circuit, and a timing signal generation circuit that receives a reference clock signal and generates a timing signal to control a timing to operate the sample and hold circuit based on the reference clock signal. The plurality of processing circuits serially execute processing in order from the processing circuit at a preceding stage to the processing circuit at a subsequent stage. The timing signal generation circuit is coupled to the plurality of processing circuits so as to supply the timing signal to each of the plurality of processing circuits in order from the processing circuit at the subsequent stage to the processing circuit at the preceding stage.

Abstract: A semiconductor integrated circuit includes a plurality of processing circuits including a sample and hold circuit, and a timing signal generation circuit that receives a reference clock signal and generates a timing signal to control a timing to operate the sample and hold circuit based on the reference clock signal. The plurality of processing circuits serially execute processing in order from the processing circuit at a preceding stage to the processing circuit at a subsequent stage. The timing signal generation circuit is coupled to the plurality of processing circuits so as to supply the timing signal to each of the plurality of processing circuits in order from the processing circuit at the subsequent stage to the processing circuit at the preceding stage.

Abstract: A solid-state imaging device includes a substrate having a rectangular shape; a first region configured to extend on the substrate in a length direction of the substrate, and to include a plurality of electrode pads arranged above the substrate through a multilayer interconnection; and a second region configured to extend in the length direction, and to include an imaging element, an optical filter, and an insulating film. The second region extends on the substrate on which the imaging element is arranged. The optical filter is arranged above the substrate and faces the imaging element through the insulating film. The second region extends in parallel to the first region to be apart from the first region by a given distance. The plurality of electrode pads are arranged to be apart from each other by a given space, equal to or smaller than the given distance, in the length direction.

Abstract: A solid-state imaging device includes a substrate having a rectangular shape; a first region configured to extend on the substrate in a length direction of the substrate, and to include a plurality of electrode pads arranged above the substrate through a multilayer interconnection; and a second region configured to extend in the length direction, and to include an imaging element, an optical filter, and an insulating film. The second region extends on the substrate on which the imaging element is arranged. The optical filter is arranged above the substrate and faces the imaging element through the insulating film. The second region extends in parallel to the first region to be apart from the first region by a given distance. The plurality of electrode pads are arranged to be apart from each other by a given space, equal to or smaller than the given distance, in the length direction.

Abstract: A sampling clock generator circuit includes a reference clock generator, a sampling hold circuit, a sampling clock generator to delay an output clock signal from the reference clock generator by a predetermined delay amount to generate and supply a sampling clock signal to the sampling hold circuit, a phase determining element to compare phases of a drive clock signal for an image reading unit and the sampling clock signal to output a result of the phase comparison, the drive clock signal generated according to the output clock signal of the reference clock generator, and a controller to adjust the delay amount of the sampling clock generator on the basis of the result of the phase comparison so that a phase difference between the drive clock signal and the sampling clock signal becomes zero.

Abstract: A sampling clock generator circuit includes a reference clock generator, a sampling hold circuit, a sampling clock generator to delay an output clock signal from the reference clock generator by a predetermined delay amount to generate and supply a sampling clock signal to the sampling hold circuit, a phase determining element to compare phases of a drive clock signal for an image reading unit and the sampling clock signal to output a result of the phase comparison, the drive clock signal generated according to the output clock signal of the reference clock generator, and a controller to adjust the delay amount of the sampling clock generator on the basis of the result of the phase comparison so that a phase difference between the drive clock signal and the sampling clock signal becomes zero.

Abstract: A communications interface apparatus includes a register, first and second memories, and a control circuit. The register circuit stores data to be transferred to a host computer. The first memory stores first information indicating a specific address of the register and representing an access to the apparatus executed by the host computer for a data transfer. The second memory stores second information, sent from the host computer in association with the first information stored in the first memory, to be written into the register at the specific address indicated by the first information stored in the first memory. The control circuit performs an information writing operation for writing the first information into the first memory and the second information into the second memory in chronological order of accesses executed.