Patents by Inventor Isamu Mochizuki

Isamu Mochizuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7247420
    Abstract: The invention concerns a lift-off process for patterning layers that are deposited and/or sputtered. The invention provides a two-layer resist and a patterning method using the resist. The patterning method can readily produce burr-free layers on a substrate. The method comprises the steps of: sequentially applying positive radiation-sensitive resin compositions 1 and 2 to form a two-layer laminate; subjecting the two-layer resist to single exposure and development to produce fine patterns having an undercut cross section; depositing and/or sputtering an organic or inorganic thin layer with use of the resist pattern as a mask; and lifting off the resist pattern to leave a pattern of the thin layer in desired shape.
    Type: Grant
    Filed: November 15, 2002
    Date of Patent: July 24, 2007
    Assignee: JSR Corporation
    Inventors: Masaru Ohta, Atsushi Ito, Isamu Mochizuki, Katsumi Inomata, Shin-ichiro Iwanaga
  • Publication number: 20040131963
    Abstract: The invention concerns a lift-off process for patterning layers that are deposited and/or sputtered. The invention provides a two-layer resist and a patterning method using the resist. The patterning method can readily produce burr-free layers on a substrate.
    Type: Application
    Filed: October 27, 2003
    Publication date: July 8, 2004
    Inventors: Masaru Ohta, Atsushi Ito, Isamu Mochizuki, Katsumi Inomata, Shin-ichiro Iwanaga
  • Patent number: 6697906
    Abstract: A semiconductor device is connected to a CPU, a memory and I/O devices to serve as a data transfer bridge for efficient data transfer between the memory and the I/O devices. A CPU interface and a plurality of I/O interfaces included in a bridge chip are connected through an internal bus to a memory interface included in the bridge chip. Each I/O interface has a read/write buffer and a DMAC. An arbiter included in the bridge chip determines a bus master for which data transfer is permitted in response to requests for data transfer from each of the CPU interface and the DMAC to the memory. Each of the I/O interfaces has a control function to skip part of areas in the memory when transferring data between the memory and the I/O interface.
    Type: Grant
    Filed: April 28, 2000
    Date of Patent: February 24, 2004
    Assignees: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Kazushige Ayukawa, Jun Sato, Takashi Miyamoto, Kenichiro Omura, Hiroyuki Hamasaki, Hiroshi Takeda, Makoto Takano, Isamu Mochizuki, Yasuhiko Hoshi, Kazuhiro Hirade, Ryuichi Murashima
  • Patent number: 6423463
    Abstract: A positive-tone photosensitive resin composition for forming a thick film which is suitably used for photofabrication such as manufacture of circuit boards, a photosensitive resin film, and a method of forming a bump using the same. The photosensitive resin composition comprising (A) a novolac resin with a weight average molecular weight of 2,000-30,000, (B) a polyvinyl lower alkyl ether, (C) a polyphenol derivative compound with a molecular weight of 200-1,000, and (D) a compound containing a naphthoquinonediazido group.
    Type: Grant
    Filed: February 29, 2000
    Date of Patent: July 23, 2002
    Assignee: JSR Corporation
    Inventors: Masaru Oota, Isamu Mochizuki, Kouichi Hirose, Yasuaki Yokoyama, Hozumi Sato
  • Patent number: 5987589
    Abstract: A microcomputer that is easy to use and connected direct to such memories as dynamic and static RAM's and to other peripheral circuits. The microcomputer has strobe signal output terminals CASH*, CASL* and RAS* for direct connection to a dynamic RAM, and chip select signal output terminals CS0* through CS6* for outputting a chip select signal in parallel with the output from the strobe signal output terminals. The microcomputer further includes address output terminals for outputting a non-multiplexed or multiplexed address signal as needed, and data I/O terminals for selectively outputting the address signal to comply with a multiple-bus interface scheme.
    Type: Grant
    Filed: October 24, 1997
    Date of Patent: November 16, 1999
    Assignees: Hitachi Ltd., Hitachi Microcomputer System Ltd., Hitachi ULSI Engineering Corp.
    Inventors: Shumpei Kawasaki, Kaoru Fukada, Mitsuru Watabe, Kouki Noguchi, Kiyoshi Matsubara, Isamu Mochizuki, Kazufumi Suzukawa, Shigeki Masumura, Yasushi Akao, Eiji Sakakibara
  • Patent number: 5748977
    Abstract: A microcomputer that is easy to use and connected direct to such memories as dynamic and static RAM's and to other peripheral circuits. The microcomputer has strobe signal output terminals CASH*, CASL* and RAS* for direct connection to a dynamic RAM, and chip select signal output terminals CS0* through CS6* for outputting a chip select signal in parallel with the output from the strobe signal output terminals. The microcomputer further includes address output terminals for outputting a non-multiplexed or multiplexed address signal as needed, and data I/O terminals for selectively outputting the address signal to comply with a multiple-bus interface scheme.
    Type: Grant
    Filed: April 4, 1996
    Date of Patent: May 5, 1998
    Assignees: Hitachi, Ltd., Hitachi Microcomputer System Ltd., Hitachi ULSI Engineering Corp.
    Inventors: Shumpei Kawasaki, Kaoru Fukada, Mitsuru Watabe, Kouki Noguchi, Kiyoshi Matsubara, Isamu Mochizuki, Kazufumi Suzukawa, Shigeki Masumura, Yasushi Akao, Eiji Sakakibara