Patents by Inventor Isamu Nagasako

Isamu Nagasako has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5345194
    Abstract: A FET comprising two or more gate pads or terminals, and a reflection type oscillator including the above-mentioned FET. In this oscillator, a dielectric resonator is connected through a coupling line to the first gate pad of the FET and an output terminal is connected to the second pad. When the drain pad of the FET is connected to ground, and a suitable value of capacitive reactance is added to the source pad, then a negative resistance -R appears on the first gate pad, and thus oscillation occurs at a resonance frequency fo of the dielectric resonator. If the load resistance value viewed from the second gate pad is set to R, the maximum oscillation output occurs.
    Type: Grant
    Filed: July 14, 1992
    Date of Patent: September 6, 1994
    Assignee: NEC Corporation
    Inventor: Isamu Nagasako
  • Patent number: 3946428
    Abstract: A semiconductor package device characterized by improved operation at ultra-high frequencies and by improved heat dissipation, includes an auxiliary metal stud mounted on a metal substrate. A semiconductor element, such as a field-effect transistor or bipolar transistor, is mounted on the auxiliary stud and has at least one electrode thereof electrically connected to the stud.
    Type: Grant
    Filed: September 17, 1974
    Date of Patent: March 23, 1976
    Assignee: Nippon Electric Company, Limited
    Inventors: Shinzo Anazawa, Seiichi Ueno, Isamu Nagasako, Tadashi Nawa, Toshiaki Irie, Shigeru Sando
  • Patent number: RE29218
    Abstract: A packaged semiconductor device for use at ultra-high frequencies is characterized by improved high frequency characteristics as a result of reduced stay capacitance and reduced energy loss. The device includes a dielectric substrate and at least two conductor layers each of which is integral and extends over the top, side, and bottom surfaces of the dielectric substrate. No part of the conductor layer on the top surface overlaps the part on the bottom surface when viewed in a direction normal to the substrate.
    Type: Grant
    Filed: October 4, 1976
    Date of Patent: May 10, 1977
    Assignee: Nippon Electric Company, Limited
    Inventors: Shinzo Anazawa, Seiichi Ueno, Isamu Nagasako, Shigeru Sando