Patents by Inventor Isamu NAKAHASHI

Isamu NAKAHASHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multiprocessor system configured as system LSI
    Patent number: 8549200
    Abstract: A multiprocessor system includes a plurality of processor units each transmitting an interrupt request signal indicating an interrupt request for which an interrupt-request destination processor unit is specified and receiving an interrupt signal and an interrupt control circuit receiving the interrupt request signal from each of the plurality of processor units and transmitting the interrupt signal to each of the plurality of processor units, wherein, the interrupt control circuit transmits the interrupt signal to the interrupt-request destination processor unit specified by the interrupt request signal if the specified interrupt-request destination processor unit is not in a low power consumption state and transmits the interrupt signal to another processor unit different from the processor unit specified by the interrupt request signal if the specified interrupt-request destination processor unit is in the low power consumption state.
    Type: Grant
    Filed: October 7, 2009
    Date of Patent: October 1, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Isamu Nakahashi, Nobuhide Takaba, Kazuki Matsuda
  • MULTIPROCESSOR SYSTEM CONFIGURED AS SYSTEM LSI
    Publication number: 20100106876
    Abstract: A multiprocessor system includes a plurality of processor units each transmitting an interrupt request signal indicating an interrupt request for which an interrupt-request destination processor unit is specified and receiving an interrupt signal and an interrupt control circuit receiving the interrupt request signal from each of the plurality of processor units and transmitting the interrupt signal to each of the plurality of processor units, wherein, the interrupt control circuit transmits the interrupt signal to the interrupt-request destination processor unit specified by the interrupt request signal if the specified interrupt-request destination processor unit is not in a low power consumption state and transmits the interrupt signal to another processor unit different from the processor unit specified by the interrupt request signal if the specified interrupt-request destination processor unit is in the low power consumption state.
    Type: Application
    Filed: October 7, 2009
    Publication date: April 29, 2010
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Isamu NAKAHASHI, Nobuhide Takaba, Kazuki Matsuda