Abstract: A semiconductor device has an active region through which current passes and an edge termination structure region. On a front surface of a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type is provided. On a surface of the first semiconductor layer, a parallel pn structure including first columns of the first conductivity type and second columns of a second conductivity type disposed to repeatedly alternate one another is provided. The second columns in the active region include first regions and second regions. A distance from the front surface of the semiconductor substrate to a bottom surface of one of the first regions is greater than a distance from the front surface of the semiconductor substrate to a bottom surface of one of the second regions.

Abstract: A semiconductor device having an active region and a voltage withstand region comprises a first semiconductor layer of a first conductive type, a second semiconductor region of a second conductive type, disposed selectively on the front side of the first semiconductor layer, a plurality of first trench contact (TC) sections disposed at a peripheral section of the active region in the second semiconductor region, being apart from one another and extending in a first direction, a second trench contact (TC) disposed at the peripheral section of the active region in the second semiconductor region, extending in the first direction and being further from the voltage withstand region than the plurality of first trench contact sections, an electric conductor layer electrically connecting together the plurality of first TC sections, and a conductive connection region disposed between the first TC sections and second TC section, having a lower resistivity than the second semiconductor region, and electrically connecti

Abstract: Provided are a semiconductor element and a semiconductor device capable of reducing possibilities of malfunctions and breakdowns due to temperature rise. A semiconductor element (50) includes a first MOS transistor (Tr1), a second MOS transistor (Tr2), and a temperature detecting element (TD) that are provided on a semiconductor substrate (SB). The first MOS transistor (Tr1) includes an n-type source region (8), an n-type first semiconductor region (21) arranged away from the source region (8) and a p-type well region (31) arranged between the source region (8) and the first semiconductor region (21). The second MOS transistor (Tr2) includes an n-type source region (8) an n-type second semiconductor region (22) arranged away from the source region (8), and a p-type well region (31) arranged between the source region (8) and the second semiconductor region (22). The first semiconductor region (21) is connected to the second semiconductor region (22).

Abstract: A semiconductor device has an active region through which current passes and an edge termination structure region. On a front surface of a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type is provided. On a surface of the first semiconductor layer, a parallel pn structure including first columns of the first conductivity type and second columns of a second conductivity type disposed to repeatedly alternate one another is provided. The second columns in the active region include first regions and second regions. A distance from the front surface of the semiconductor substrate to a bottom surface of one of the first regions is greater than a distance from the front surface of the semiconductor substrate to a bottom surface of one of the second regions.

Abstract: A semiconductor device having an active region and a voltage withstand region comprises a first semiconductor layer of a first conductive type, a second semiconductor region of a second conductive type, disposed selectively on the front side of the first semiconductor layer, a plurality of first trench contact (TC) sections disposed at a peripheral section of the active region in the second semiconductor region, being apart from one another and extending in a first direction, a second trench contact (TC) disposed at the peripheral section of the active region in the second semiconductor region, extending in the first direction and being further from the voltage withstand region than the plurality of first trench contact sections, an electric conductor layer electrically connecting together the plurality of first TC sections, and a conductive connection region disposed between the first TC sections and second TC section, having a lower resistivity than the second semiconductor region, and electrically connecti

Abstract: In each n-type epitaxial layer, p-type impurity regions are respectively formed by performing for each stacking of an n-type epitaxial layer, ion implantation using a resist mask. In a first n-type epitaxial layer, a p-type impurity region is formed at an inner wall of an impurity diffusion trench formed by dry etching. In a second and third n-type epitaxial layer, p-type impurity regions are formed respectively at an inner wall of impurity diffusion trenches that are recesses respectively corresponding to the impurity diffusion trenches of the first and the second n-type epitaxial layers respectively therebelow. The resist mask has an opening width that is wider than widths of open ends of the impurity diffusion trenches. The p-type impurity regions are connected by thermal diffusion processing, thereby forming a parallel pn layer constituted by p-type regions having a high aspect ratio and n-type regions respectively between the p-type regions.

Abstract: Provided are a semiconductor element and a semiconductor device capable of reducing possibilities of malfunctions and breakdowns due to temperature rise. A semiconductor element (50) includes a first MOS transistor (Tr1), a second MOS transistor (Tr2), and a temperature detecting element (TD) that are provided on a semiconductor substrate (SB). The first MOS transistor (Tr1) includes an n-type source region (8), an n-type first semiconductor region (21) arranged away from the source region (8) and a p-type well region (31) arranged between the source region (8) and the first semiconductor region (21). The second MOS transistor (Tr2) includes an n-type source region (8) an n-type second semiconductor region (22) arranged away from the source region (8), and a p-type well region (31) arranged between the source region (8) and the second semiconductor region (22). The first semiconductor region (21) is connected to the second semiconductor region (22).

Abstract: In each n-type epitaxial layer, p-type impurity regions are respectively formed by performing for each stacking of an n-type epitaxial layer, ion implantation using a resist mask. In a first n-type epitaxial layer, a p-type impurity region is formed at an inner wall of an impurity diffusion trench formed by dry etching. In a second and third n-type epitaxial layer, p-type impurity regions are formed respectively at an inner wall of impurity diffusion trenches that are recesses respectively corresponding to the impurity diffusion trenches of the first and the second n-type epitaxial layers respectively therebelow. The resist mask has an opening width that is wider than widths of open ends of the impurity diffusion trenches. The p-type impurity regions are connected by thermal diffusion processing, thereby forming a parallel pn layer constituted by p-type regions having a high aspect ratio and n-type regions respectively between the p-type regions.

Abstract: An n-type region and a p-type region of a first parallel pn layer are arranged parallel to a base front surface, in a striped planar layout extending from an active region over an edge termination region. In the n-type region, a gate trench extending linearly along a first direction is provided. In an intermediate region, in a surface region on the base front surface side of the first parallel pn layer, a second parallel pn layer is provided. The second parallel pn layer is arranged having a repetition cycle shifted along a second direction ½ a cell with respect to a repetition cycle of the n-type region and the p-type region of the first parallel pn layer. A gate trench termination portion terminates in the intermediate region between the active region and the edge termination region, and is covered by the p-type region of the second parallel pn layer.

Abstract: To provide a semiconductor device having a structure capable of forming a superjunction with less thermal history, a semiconductor device is provided, the semiconductor device including a contact trench formed between two gate trenches, penetrating through a source region, and including its lower end arranged in a base region, and a second conductivity-type protruding portion formed protruding toward a lower side from the lower end of the base region in a region opposite to the lower end of the contact trench, wherein the depth from the upper end of the source region to a lower end of the protruding portion is 3 ?m or more, and a carrier concentration Nd in a first conductivity-type region adjacent to the protruding portion in a lateral direction perpendicular to a depth direction and a carrier concentration Na of the protruding portion satisfy a predetermined equation.

Abstract: An n-type region and a p-type region of a first parallel pn layer are arranged parallel to a base front surface, in a striped planar layout extending from an active region over an edge termination region. In the n-type region, a gate trench extending linearly along a first direction is provided. In an intermediate region, in a surface region on the base front surface side of the first parallel pn layer, a second parallel pn layer is provided. The second parallel pn layer is arranged having a repetition cycle shifted along a second direction ½ a cell with respect to a repetition cycle of the n-type region and the p-type region of the first parallel pn layer. A gate trench termination portion terminates in the intermediate region between the active region and the edge termination region, and is covered by the p-type region of the second parallel pn layer.

Abstract: An n-type region and a p-type region of a first parallel pn layer are arranged parallel to a base front surface, in a striped planar layout extending from an active region over an edge termination region. In the n-type region, a gate trench extending linearly along a first direction is provided. In an intermediate region, in a surface region on the base front surface side of the first parallel pn layer, a second parallel pn layer is provided. The second parallel pn layer is arranged having a repetition cycle shifted along a second direction ½ a cell with respect to a repetition cycle of the n-type region and the p-type region of the first parallel pn layer. A gate trench termination portion terminates in the intermediate region between the active region and the edge termination region, and is covered by the p-type region of the second parallel pn layer.

Abstract: To provide a semiconductor device having a structure capable of forming a superjunction with less thermal history, a semiconductor device is provided, the semiconductor device including a contact trench formed between two gate trenches, penetrating through a source region, and including its lower end arranged in a base region, and a second conductivity-type protruding portion formed protruding toward a lower side from the lower end of the base region in a region opposite to the lower end of the contact trench, wherein the depth from the upper end of the source region to a lower end of the protruding portion is 3 ?m or more, and a carrier concentration Nd in a first conductivity-type region adjacent to the protruding portion in a lateral direction perpendicular to a depth direction and a carrier concentration Na of the protruding portion satisfy a predetermined equation.

Abstract: To provide an optimal structure for electrically connecting an MOSFET region, a FWD region, and an IGBT region in parallel within one semiconductor chip by mitigating electric field concentration between a SJ column and a drift region, a semiconductor device is provided, the semiconductor device including: a semiconductor substrate: a super junction MOSFET having a repetitive structure of a first column and a second column; a parallel device having a drift region including second conductivity-type impurities, and being provided separately from the super junction MOSFET in the semiconductor substrate; and a boundary portion located between the super junction MOSFET and the parallel device in the semiconductor substrate, wherein the boundary portion extends from one main surface side to the other main surface side, and has at least one third column having first conductivity-type impurities, and the third column is shallower than the first column and the second column.

Abstract: To provide a semiconductor device having a structure capable of forming a superjunction with less thermal history, a semiconductor device is provided, the semiconductor device including a contact trench formed between two gate trenches, penetrating through a source region, and including its lower end arranged in a base region, and a second conductivity-type protruding portion formed protruding toward a lower side from the lower end of the base region in a region opposite to the lower end of the contact trench, wherein the depth from the upper end of the source region to a lower end of the protruding portion is 3 ?m or more, and a carrier concentration Nd in a first conductivity-type region adjacent to the protruding portion in a lateral direction perpendicular to a depth direction and a carrier concentration Na of the protruding portion satisfy a predetermined equation.

Abstract: An n-type region and a p-type region of a first parallel pn layer are arranged parallel to a base front surface, in a striped planar layout extending from an active region over an edge termination region. In the n-type region, a gate trench extending linearly along a first direction is provided. In an intermediate region, in a surface region on the base front surface side of the first parallel pn layer, a second parallel pn layer is provided. The second parallel pn layer is arranged having a repetition cycle shifted along a second direction ½ a cell with respect to a repetition cycle of the n-type region and the p-type region of the first parallel pn layer. A gate trench termination portion terminates in the intermediate region between the active region and the edge termination region, and is covered by the p-type region of the second parallel pn layer.

Abstract: To provide a semiconductor device having a structure capable of forming a superjunction with less thermal history, a semiconductor device is provided, the semiconductor device including a contact trench formed between two gate trenches, penetrating through a source region, and including its lower end arranged in a base region, and a second conductivity-type protruding portion formed protruding toward a lower side from the lower end of the base region in a region opposite to the lower end of the contact trench, wherein the depth from the upper end of the source region to a lower end of the protruding portion is 3 ?m or more, and a carrier concentration Nd in a first conductivity-type region adjacent to the protruding portion in a lateral direction perpendicular to a depth direction and a carrier concentration Na of the protruding portion satisfy a predetermined equation.

Abstract: To provide an optimal structure for electrically connecting an MOSFET region, a FWD region, and an IGBT region in parallel within one semiconductor chip by mitigating electric field concentration between a SJ column and a drift region, a semiconductor device is provided, the semiconductor device including: a semiconductor substrate: a super junction MOSFET having a repetitive structure of a first column and a second column; a parallel device having a drift region including second conductivity-type impurities, and being provided separately from the super junction MOSFET in the semiconductor substrate; and a boundary portion located between the super junction MOSFET and the parallel device in the semiconductor substrate, wherein the boundary portion extends from one main surface side to the other main surface side, and has at least one third column having first conductivity-type impurities, and the third column is shallower than the first column and the second column.

Abstract: A perpendicular magnetic recording medium is disclosed in which crystal axis orientation dispersion, crystal grain diameter, and crystal grain diameter dispersion in a magnetic recording layer are reduced. The perpendicular magnetic recording medium has a structure having, stacked sequentially on a non-magnetic substrate, at least an amorphous underlayer, a lower orientation control layer made of Ru or Ru alloy of an hcp structure, an upper orientation control layer that is made of alloy containing an element selected from the group consisting of Co and Ni and an element selected from the group consisting of Cr, W, and Mo and that has an fcc or hcp structure, an intermediate layer, and a magnetic recording layer.

Abstract: A perpendicular magnetic recording medium is disclosed in which crystal axis orientation dispersion, crystal grain diameter, and crystal grain diameter dispersion in a magnetic recording layer are reduced. The perpendicular magnetic recording medium has a structure having, stacked sequentially on a non-magnetic substrate, at least an amorphous underlayer, a lower orientation control layer made of Ru or Ru alloy of an hcp structure, an upper orientation control layer that is made of alloy containing an element selected from the group consisting of Co and Ni and an element selected from the group consisting of Cr, W, and Mo and that has an fcc or hcp structure, an intermediate layer, and a magnetic recording layer.