Patents by Inventor Isamu Yamazaki

Isamu Yamazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9505014
    Abstract: A rotary atomizing head enables cleaning by decomposing from the atomizing head, and enables internal cleaning without decomposing to individual components when paint is changed to a new one of another color. A structural component has a front wall acting as a hub, side wall extending rearward from an outer circumferential perimeter of the front wall to make a circumferentially continuous plane, legs each having a pawl and a bottom wall. The structural component is detachably mounted in a central concavity of an atomizing head body. A bottom wall of the structural component has formed a spoon-cut recess. The central concavity has an inclined circumferential wall, and the side wall of the structural component has an inclined outer circumferential surface complementary with the circumferential wall of the atomizing head body to get in substantial contact with the circumferential wall throughout the entire area of the outer circumferential wall.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: November 29, 2016
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, RANSBURG INDUSTRIAL FINISHING K.K.
    Inventors: Michio Mitsui, Ryuji Tani, Isamu Yamazaki, Toru Yokota
  • Publication number: 20040221376
    Abstract: Swimming goggles improved so that a visual line of a swimming goggles wearer may be easily directed forward during competitive swimming. Each lens of swimming goggles is divided into an intermediate section extending across the lens at a generally middle level as viewed in a vertical direction, an upper section lying above the intermediate section and a lower section lying below the intermediate section. The intermediate section presents a see-through clarity lower than those presented by the upper section and the lower section.
    Type: Application
    Filed: February 27, 2004
    Publication date: November 11, 2004
    Inventors: Haruo Kawashima, Shunji Fukasawa, Isamu Yamazaki
  • Patent number: 6612345
    Abstract: An apparatus for replenishing paint into a paint cartridge (25), which is capable of putting paint in respiratory circulation while the cartridge is in a waiting state. The apparatus includes a replenishing valve (61) which is capable of feeding paint to and from a paint chamber (30) of the paint cartridge (25) which is set on a replenishing stool (52), and a respiratory paint circulation valve (91) which is capable of feeding paint-extruding thinner to and from a thinner chamber (31) of the cartridge. After switching the replenishing valve (61) to a drain or discharge side, paint-extruding thinner is supplied from the respiratory paint circulation valve (91) to push paint out of the paint chamber (30) of the cartridge (25). Then, after switching the replenishing valve (61) to the side of a paint supply source, paint-extruding thinner is discharged by way of the respiratory paint circulation valve (91) to suck paint into the paint chamber (30).
    Type: Grant
    Filed: January 4, 2001
    Date of Patent: September 2, 2003
    Assignee: ABB K.K.
    Inventors: Toshio Hosoda, Tomoaki Takeda, Shinji Tani, Kimio Toda, Takanobu Mori, Isamu Yamazaki
  • Patent number: 5662637
    Abstract: A disposable absorbent article such as a disposable diaper including first stretchable side flaps extending over transversely opposite outer zones of the diaper and second stretchable side flaps functioning as liquid-barriers each having a proximal edge and a distal edge arranged so as to define an exposed zone of a topsheet along each of transversely opposite side edge surfaces of a liquid-absorbent core and thereby, if a quantity of liquid excretions gets over the distal edge of the second side flaps, it can be absorbed by the liquid-absorbent core through the exposed zones.
    Type: Grant
    Filed: November 30, 1994
    Date of Patent: September 2, 1997
    Assignee: Uni-Charm Corporation
    Inventors: Hideaki Kitaoka, Isamu Yamazaki, Makoto Suekane
  • Patent number: 5596682
    Abstract: A method of automated theorem proving for information processing which can be highly efficient, irrespective of the set of clauses to be dealt with. The method includes the steps of: transforming the statement and the set of knowledge into expressions in terms of elements of a module; constructing a linear equation with the elements of the module as coefficients and the elements of a ring of scalars of the module as unknowns; checking the existence of a non-negative solution to the linear equation; and determining that the statement is provable when the non-negative solution exist, and not provable otherwise.
    Type: Grant
    Filed: January 21, 1994
    Date of Patent: January 21, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Isamu Yamazaki
  • Patent number: 4910508
    Abstract: A matrix logic circuit network comprises a great number of interconnected logic gates. Input and output lines of the logic gates are arranged in the matrix array. By rearranging the input and output lines of the matrix in accordance with a sort algorithm, direct connection points of the input and output lines to which the same signals are allotted and connecting elements forming logic gates located at given intersections of the input and output lines are arranged within a diagonal area with a limited width, which extends along a diagonal line of the matrix.
    Type: Grant
    Filed: December 16, 1985
    Date of Patent: March 20, 1990
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventor: Isamu Yamazaki
  • Patent number: 4823258
    Abstract: The vector processor of the present invention is designed to have a first function for classifying, generating and storing in advance a separate index set by judging the attribute of specified data and a second function for continuously performing operand access only for the index value belonging to the specified index set out of the index sets generated by the first function, thus avoiding the deterioration of the efficiency of pipeline processing even when the calculation of array data has different operation content according to the attributes of the specified data. Accordingly it can perform continuous calculation of a plurality of different conditioned expressions at high speed by arranging it to operate the first and the second functions concurrently with the value resulting from the operation by the second function being used by the first function as a data for discriminating the attribute of the data.
    Type: Grant
    Filed: September 18, 1987
    Date of Patent: April 18, 1989
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventor: Isamu Yamazaki
  • Patent number: 4763827
    Abstract: The invention relates to a manufacturing apparatus which comprises moving means which continuously moves the works that are transferred along a frame chute, and detector means which detects at least a portion of the work that is moved. The moving means is controlled by kind-of-work data and by a work position signal from the detector means, and the work is set to a predetermined position. Hence, even a work of a different kind can be set to an optimum bonding position without the need of exchanging the unit, making it possible to perform the operation fully automatically and to meet general purposes.Further, provision is made of means which moves the frame chute in a direction at right angles with the direction in which the work is moved, so that even that work that has different widths and shapes in the widthwise direction can be placed in position and subjected to the bonding fully automatically.
    Type: Grant
    Filed: April 16, 1987
    Date of Patent: August 16, 1988
    Assignees: Hitachi, Ltd., Hitachi Tokyo Electronics
    Inventors: Kenji Watanabe, Isamu Yamazaki, Ryuichi Kyomasu, Nobuhiro Takasugi, Tsutomu Mimata, Osamu Kakutani
  • Patent number: 4734849
    Abstract: In a one-chip high density arithmetic control unit capable of prefetching user's instructions from main memory, an arithmetic logic unit (ALU) subtracts the contents of a location counter holding the address of the next instruction to be executed, from the contents of a memory address register holding an address into which data will be written. The difference is fed through the gates connected to the ALU for determining whether or not prefetched instructions will have to be refetched. An address matching mechanism provided outside the one-chip arithmetic control unit includes a comparator for comparing memory addresses to a preset execution stop address.
    Type: Grant
    Filed: July 16, 1986
    Date of Patent: March 29, 1988
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Tsuneo Kinoshita, Fumitaka Sato, Isamu Yamazaki
  • Patent number: 4674670
    Abstract: The invention relates to a manufacturing apparatus which comprises moving means which continuously moves the works that are transferred along a frame chute, and detector means which detects at least a portion of the work that is moved. The moving means is controlled by kind-of-work data and by a work position signal from the detector means, and the work is set to a predetermined position. Hence, even a work of a different kind can be set to an optimum bonding position without the need of exchanging the unit, making it possible to perform the operation fully automatically and to meet general purposes.Further, provision is made of means which moves the frame chute in a direction at right angles with the direction in which the work is moved, so that even that work that has different widths and shapes in the widthwise direction can be placed in position and subjected to the bonding fully automatically.
    Type: Grant
    Filed: August 6, 1985
    Date of Patent: June 23, 1987
    Assignees: Hitachi, Ltd., Hitachi Tokyo Engineering Co., Ltd.
    Inventors: Kenji Watanabe, Isamu Yamazaki, Ryuichi Kyomasu, Nobuhiro Takasugi, Tsutomu Mimata, Osamu Kakutani
  • Patent number: 4616331
    Abstract: In a one-chip high density arithmetic control unit capable of prefetching user's instructions from main memory, an arithmetic logic unit (ALU) subtracts the contents of a location counter holding the address of the next instruction to be executed, from the contents of a memory address register holding an address into which data will be written. The difference is fed through the gates connected to the ALU for determining whether or not prefetched instructions will have to be refetched. An address matching mechanism provided outside the one-chip arithmetic control unit includes a comparator for comparing memory addresses to a preset execution stop address.
    Type: Grant
    Filed: February 19, 1981
    Date of Patent: October 7, 1986
    Inventors: Tsuneo Kinoshita, Fumitaka Sato, Isamu Yamazaki
  • Patent number: 4472788
    Abstract: A shift circuit comprises a plurality of stages of data selectors, a first data selector, a second data selector and a temporary register. The data selectors shift an n-bit input data by m bits which are specified by a shifting amount data and produces a first output data or a second output data. The first and second data selectors selectively output the first and second output data in accordance with shift direction. The temporary register comprises n bits for storing a data which is not selected by said first or second data selector.
    Type: Grant
    Filed: August 27, 1981
    Date of Patent: September 18, 1984
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventor: Isamu Yamazaki
  • Patent number: 4466055
    Abstract: In an information processing system in which an arithmetic control unit is formed on one chip by very large scale integration and is connected to external devices by a common bus, microinstructions from an externally-connected control memory, memory information output from an external main memory and information output from I/O devices, can be received by the arithmetic control unit on the common bus. An external setting signal for selecting whether the instruction system of the arithmetic control unit is to be enabled or disabled is input to the arithmetic control unit on the common bus simultaneously with the fetching of a microinstruction. A bus width setting signal from an I/O device is also input to the arithmetic control unit on the common bus simultaneously with the fetching of a microinstruction, and the CPU determines whether the data width of an I/O device is 8 bits or 16 bits.
    Type: Grant
    Filed: March 17, 1981
    Date of Patent: August 14, 1984
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Tsuneo Kinoshita, Fumitaka Sato, Isamu Yamazaki
  • Patent number: 4291334
    Abstract: An apparatus for detecting the position of an object. The apparatus has an optical device for magnifying or enlarging a plurality of portions on the object, a photoelectric converter adapted for converting the enlarged portion image into electric signals, a plurality of thresholding circuits adapted for changing analogue signals from the respective photoelectric converter into binary signals with a threshold value determined by a signal level given by a first signal holding circuit, a circuit for calculating the threshold value from the analogue signals, a circuit for detecting the approximate position of a specific pattern in the enlarged portion images through a coarse sampling of the binary signals. A circuit for detecting the exact position of the specific pattern through measuring the area of a specific brightness in a plurality of regions in the enlarged portion images, by a fine sampling of the binary signals, and a controller for controlling the operations of respective circuits.
    Type: Grant
    Filed: May 17, 1977
    Date of Patent: September 22, 1981
    Assignee: Hitachi, Ltd.
    Inventors: Michihiro Mese, Seiji Kashioka, Masakazu Ejiri, Takafumi Miyatake, Isamu Yamazaki, Toshimitsu Hamada
  • Patent number: 4195344
    Abstract: A computer system in which the configuration of a plurality of information processing modules, which are provided in at least first and second configuration points, may be automatically monitored and supervised, comprises a plurality of switching modules provided in a third configuration point, each switching module having a configuration point number and each of the information processing modules having an identification number; and a configuration monitoring center for at least monitoring the connecting conditions between the switching modules and the configuration monitoring center for supervision of the computer system. Timing signals are delivered from the configuration monitoring center to inquire about conditions in the information processing modules and switching modules.
    Type: Grant
    Filed: April 4, 1978
    Date of Patent: March 25, 1980
    Assignee: The President of the Agency of Industrial Science and Technology
    Inventor: Isamu Yamazaki
  • Patent number: 4179731
    Abstract: A microprogrammed control system comprises: a memory for storing a microprogram programmed with microinstructions; a memory for storing microinstructions for branching microinstruction; an address register for storing the address of the microinstruction to be next executed; and a microinstruction register for storing the microinstruction to be executed. The program operation of the microprogrammed control system depends on whether the micro-instruction stored in the microinstruction register is the branching one or not. In the case of non-branching microinstruction, the operation of ordinary microinstructions is executed. In the case of branching microinstruction, a special operation is executed for making the operation of the branching microinstruction equivalent to that of the ordinary microinstruction.
    Type: Grant
    Filed: April 4, 1977
    Date of Patent: December 18, 1979
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventor: Isamu Yamazaki
  • Patent number: 4130869
    Abstract: A microprogram controlled system to which is applied the vertical type microprogramming technique. Microinstructions fetched from a control stage are decoded in a control decoder, which controls gates of registers in a central processor to execute the microinstructions. The microinstructions include an extension field in the format to modify the functions thereof.
    Type: Grant
    Filed: March 21, 1977
    Date of Patent: December 19, 1978
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventors: Tsuneo Kinoshita, Isamu Yamazaki
  • Patent number: 4126896
    Abstract: A microprogrammed LSI microprocessor comprises a read only memory (ROM) for storing therein microprograms and a decode table for the operation code of macroinstructions, and an arithmetic logic control section constructed into a one package of LSI circuit. The arithmetic logic control section is constructed into a circuit arrangement which, on the assumption that the operation code of macroinstructions be an address, sets the starting address of a corresponding macroinstruction read from the ROM in a location counter, reads from the ROM a microinstruction corresponding to the starting address set in the location counter to set this microinstruction in a microinstruction register, and arithmetically executes the microinstruction stored in the microinstruction register.
    Type: Grant
    Filed: April 1, 1977
    Date of Patent: November 21, 1978
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventor: Isamu Yamazaki
  • Patent number: 4091394
    Abstract: A pattern position detecting system comprising first means to sequentially fetch local images in a two-dimensionally arrayed form from a video signal in accordance with the scanning of an image and at sampling intervals which are variably instructed independently in the vertical and horizontal directions, second means to hold two-dimensional patterns having the same array as the local images, third means to evaluate the degree of non-coincidence between the image of the first means and the pattern of the second means, fourth means to store the position of an image scanning point at the time when the degree of non-coincidence becomes the minimum in a predetermined range within a picture frame, fifth means to calculate the position of an object from the position obtained by the fourth means, and sixth means to store the vertical and horizontal sampling intervals necessary for the operation of the first means, the two-dimensional patterns for use in the second means and numerical values necessary for the positio
    Type: Grant
    Filed: January 26, 1977
    Date of Patent: May 23, 1978
    Assignee: Hitachi, Ltd.
    Inventors: Seiji Kashioka, Masakazu Ejiri, Michihiro Mese, Takafumi Miyatake, Toshimitsu Hamada, Isamu Yamazaki
  • Patent number: 4057680
    Abstract: In the method of polymerizing .alpha.-olefins by contacting an .alpha.-olefin under polymerization conditions with a stereospecific catalyst comprising a titanium trichloride component and an organoaluminium compound, the improvement wherein said titanium trichloride component is ground during or after contact with a treating agent, said treating agent being selected from at least one ofA. an alkylene oxide, andB. a lactone.
    Type: Grant
    Filed: August 10, 1976
    Date of Patent: November 8, 1977
    Assignee: Showa Denko Kabushiki Kaisha
    Inventors: Isamu Yamazaki, Yoichi Toyama, Kiwami Hirota, Hisashi Takeuchi