Patents by Inventor Isao Ashida

Isao Ashida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7109500
    Abstract: A mask pattern correction method capable of preventing a position of a pattern from deviating by deformation of a mask due to gravity, a mask production method, a mask, and a production method of a semiconductor device capable of forming a fine pattern with high accuracy are provided.
    Type: Grant
    Filed: March 20, 2003
    Date of Patent: September 19, 2006
    Assignee: Sony Corporation
    Inventors: Shinji Omori, Kaoru Koike, Shigeru Moriya, Isao Ashida
  • Publication number: 20060143172
    Abstract: Based on design data 151 and mask characteristic data 152 indicating at least the characteristics of a complementary stencil mask, generating alignment marks, designing membrane shapes, performing PUF division and boundary processing, complementarily dividing the mask, stitching, arranging complementary patterns, verifying pattern shapes, making corrections in the membrane, configuring the mask, verifying exposure, making corrections by inverting the mask, verifying the results of correction, converting the data, and thereby generating the drawing membrane data and drawing pattern data.
    Type: Application
    Filed: February 4, 2004
    Publication date: June 29, 2006
    Inventors: Isao Ashida, Kohichi Nakayama
  • Patent number: 7010434
    Abstract: A complementary division condition determining method and program and a complementary division method able to propose the optimum complementary division conditions for suppressing pattern displacement and mask destruction, wherein an internal stress of a mask is determined based on a displacement of a peripheral mark in a case when forming an opening in the mask and this value is used for first analysis (step ST12), pattern displacement and stress concentration occurring due to openings of split patterns are analyzed based on a first analysis model in a first analysis (step ST13), and a displacement due to external force of the membrane between the split patterns is analyzed in a second analysis (step ST14).
    Type: Grant
    Filed: April 8, 2004
    Date of Patent: March 7, 2006
    Assignee: Sony Corporation
    Inventors: Isao Ashida, Kohichi Nakayama
  • Publication number: 20050124078
    Abstract: A mask pattern correction method capable of preventing a position of a pattern from deviating by deformation of a mask due to gravity, a mask production method, a mask, and a production method of a semiconductor device capable of forming a fine pattern with high accuracy are provided.
    Type: Application
    Filed: March 20, 2003
    Publication date: June 9, 2005
    Applicant: Sony Corp.
    Inventors: Shinji Omori, Kaoru Koike, Shigeru Moriya, Isao Ashida
  • Publication number: 20050003282
    Abstract: A stencil mask is disclosed which can be produced by performing pattern correction in a practically applicable comparatively short period of time. When stencil mask pattern data are corrected by a stress analysis, displacement amounts are calculated for those of stencil hole patterns which have a size equal to or greater than a predetermined size. As a result, stencil mask pattern data having corrected patterns are obtained in a comparatively short period of time which can be applied industrially. By producing a stencil mask based on the patterns, a stencil mask in which a desired pattern is formed is obtained.
    Type: Application
    Filed: July 30, 2004
    Publication date: January 6, 2005
    Inventor: Isao Ashida
  • Publication number: 20040210423
    Abstract: A complementary division condition determining method and program and a complementary division method able to propose the optimum complementary division conditions for suppressing pattern displacement and mask destruction, wherein an internal stress of a mask is determined based on a displacement of a peripheral mark in a case when forming an opening in the mask and this value is used for first analysis (step ST12), pattern displacement and stress concentration occurring due to openings of split patterns are analyzed based on a first analysis model in a first analysis (step ST13), and a displacement due to external force of the membrane between the split patterns is analyzed in a second analysis (step ST14). The order of the first and second analyses is not important.
    Type: Application
    Filed: April 8, 2004
    Publication date: October 21, 2004
    Inventors: Isao Ashida, Kohichi Nakayama
  • Patent number: 6780659
    Abstract: A stencil mask is disclosed which can be produced by performing pattern correction in a practically applicable comparatively short period of time. When stencil mask pattern data are corrected by a stress analysis, displacement amounts are calculated for those of stencil hole patterns which have a size equal to or greater than a predetermined size. As a result, stencil mask pattern data having corrected patterns are obtained in a comparatively short period of time which can be applied industrially. By producing a stencil mask based on the patterns, a stencil mask in which a desired pattern is formed is obtained.
    Type: Grant
    Filed: July 1, 2002
    Date of Patent: August 24, 2004
    Assignee: Sony Corporation
    Inventor: Isao Ashida
  • Patent number: 6658641
    Abstract: An object of the present invention is to accurately verify errors, etc., in programs when corrections of mask data are carried out by the programs. In order to correct the mask data based on predetermined conditions, a method for mask data verification according to the present invention comprises the steps of preparing corrected mask data by using a plurality of programs each of which has a different algorithm, comparing each of corrected mask data which is prepared in the previous step and as a result of the comparison, if there are differences among the corrected mask data, extracting errors which cause problems as mask data from the differences.
    Type: Grant
    Filed: October 17, 2001
    Date of Patent: December 2, 2003
    Inventors: Isao Ashida, Kazuhisa Ogawa
  • Publication number: 20030022496
    Abstract: A stencil mask is disclosed which can be produced by performing pattern correction in a practically applicable comparatively short period of time. When stencil mask pattern data are corrected by a stress analysis, displacement amounts are calculated for those of stencil hole patterns which have a size equal to or greater than a predetermined size. As a result, stencil mask pattern data having corrected patterns are obtained in a comparatively short period of time which can be applied industrially. By producing a stencil mask based on the patterns, a stencil mask in which a desired pattern is formed is obtained.
    Type: Application
    Filed: July 1, 2002
    Publication date: January 30, 2003
    Inventor: Isao Ashida
  • Patent number: 6401235
    Abstract: The invention provides a method and an apparatus for producing an exposure mask by which an exposure mask can be produced in a reduced production period and with a high degree of reliability. Data division which does not have an influence on a pattern of an exposure mask is indicated, and indication data which include a predetermined index code is retrieved from layout data to produce a file. Then, the layout data are divided in accordance with the file, and for each of the divided layout data, a corresponding one of processes is selectively performed in accordance with a condition. EB files produced by such processes are unified in accordance with the file to produce a plotting job.
    Type: Grant
    Filed: May 21, 1998
    Date of Patent: June 4, 2002
    Assignee: Sony Corporation
    Inventor: Isao Ashida
  • Publication number: 20020066069
    Abstract: An object of the present invention is to accurately verify errors, etc. in programs when corrections of mask data are carried out by the programs. In order to correct the mask data based on predetermined conditions, a method for mask data verification according to the present invention comprises the steps of preparing corrected mask data by using a plurality of programs each of which has a different algorism, comparing each of corrected mask data which is prepared in the previous step and as a result of the comparison, if there are differences among the corrected mask data, extracting errors which cause troubles as mask data from the differences.
    Type: Application
    Filed: October 17, 2001
    Publication date: May 30, 2002
    Applicant: Sony Corporation
    Inventors: Isao Ashida, Kazuhisa Ogawa