Abstract: A semiconductor memory device including a plurality of level converters, each of the level converters including a bridge circuit constituted by four MOS transistors having one type of conductivity, gates of one pair of four transistors opposing each other receiving a first signal and gates of the other pair of four transistors opposing each other receiving a signal complementary to the first signal; a pair of complementary MOS inverter circuits to which a second signal and a signal complementary to the second signal are input, respectively, the outputs of the pair of inverter circuits being connected to a first pair of connecting points positioned alternately in the bridge circuit, respectively; and a flip-flop circuit connected between a second pair of connecting points positioned alternately in the bridge circuit, to thereby output a third signal and a signal complementary to the third signal from the second pair of connecting points, resepctively.

Abstract: A bipolar-complementary metal oxide semiconductor circuit includes a p-channel MOS transistor, and an n-channel MOS transistor, first and second bipolar transistors. A base of the first bipolar transistor is connected to a negative power source through the n-channel MOS transistor. A diode is connected to the base and emitter of the first bipolar transistor. The diode functions to prevent a reverse-biased voltage exceeding a base-emitter breakdown voltage from being applied between the base and emitter of the first bipolar transistor.

Abstract: A bipolar-transistor type semiconductor memory device including a normal memory cell array, redundancy memory cell array, a redundancy driving circuit, and a redundancy address decision circuit. When the redundancy address decision circuit determines that the input address coincides with the address of a defective circuit portion, the redundancy driving circuit is driven to enable the redundancy memory cell array instead of the normal memory cell array.

Abstract: A semiconductor memory device includes a redundancy circuit having upper address bit input terminals receiving upper address bit, lower address bit input terminals receiving lower address bits, a regular memory cell array having a plurality of word lines and bit lines, and a plurality of memory cells are arranged at each intersection of the word and bit lines. A redundancy memory cell array is provided having a plurality of word and bit lines, and a plurality of memory cells are arranged at each intersection of the word and bit lines. The capacity of the redundancy memory cell array being smaller than the regular memory cell array. A first selection circuit selects a word or bit line in the regular memory cell array in accordance with the upper and lower address bits. A second selection circuit select a word or bit line in the redundancy memory cell array in accordance with the lower address bits.

Abstract: A bipolar-transistor type RAM device, particularly an ECL type RAM device, includes a memory cell array, an address receiving circuit, a normal memory cell selecting circuit, and a redundancy configuration. The redundancy configuration includes a redundancy memory cell array, a defective memory address storing circuit, an address comparing circuit, and a redundancy memory cell selecting circuit. The address comparing circuit directly receives the address signal and the defective memory address signal. The normal memory cell selecting circuit is energized when the address signal does not equal the defective memory address signal. Otherwise, the redundancy memory cell selecting circuit is energized.

Abstract: A semiconductor memory device used as a bipolar random access memory including a plurality of pairs of word lines, a plurality of pairs of bit lines, and a plurality of static memory cells located at the intersections of and connected between the pairs of word and bit lines. A plurality of constant current sources are selectively connected to the bit lines. A reading-writing voltage control circuit controls the potential of each bit line during the reading and writing of data and a writing current control circuit controls the current flowing to each bit line during the writing of data into the memory cell. Further, the writing current control circuit connects the constant current source to the reading-writing voltage control circuit in the writing of data to the memory cell. Accordingly, the bipolar random access memory can operate at a high speed with reduced power consumption and without unnecessary current flowing in the peripheral circuits.