Patents by Inventor Isao Houda

Isao Houda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11609267
    Abstract: Provided is an immunity evaluation system that enables design feedback in consideration of a subject wiring and an improvement amount for improving an electromagnetic noise resistance of a circuit board. An immunity evaluation device includes: a storage unit configured to store characteristic data including probe-circuit board wiring coupling characteristics which are determined by a combination of a near-field probe and circuit board characteristics, and a test result; and an IC reaching signal level estimation unit configured to estimate a signal level reaching a terminal of an evaluation target IC. The immunity evaluation device receives board design information, information of the near-field probe, and test waveform instruction information of a signal applied to the near-field probe.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: March 21, 2023
    Assignee: Hitachi, Ltd.
    Inventors: Isao Houda, Aya Ohmae, Umberto Paoletti
  • Publication number: 20220271683
    Abstract: A power conversion device including: a circuit board including a first ground constituting a ground of a first circuit and a second ground formed to be electrically separated from the first ground; a second circuit in which a joining portion is formed; a metal base plate provided between the second circuit and the circuit board and provided with an opening portion corresponding to the joining portion; and a housing that stores the circuit board, the second circuit, and the metal base plate and is electrically connected to the second ground of the circuit board and the metal base plate, in which the joining portion of the second circuit is disposed corresponding to the second ground via the opening portion of the metal base plate.
    Type: Application
    Filed: April 20, 2020
    Publication date: August 25, 2022
    Applicant: HITACHI ASTEMO, LTD.
    Inventors: Isao HOUDA, Hiroki FUNATO, Yuta NUMAKURA, Yoichiro FURUTA
  • Publication number: 20220268836
    Abstract: Provided is an immunity evaluation system that enables design feedback in consideration of a subject wiring and an improvement amount for improving an electromagnetic noise resistance of a circuit board. An immunity evaluation device includes: a storage unit configured to store characteristic data including probe-circuit board wiring coupling characteristics which are determined by a combination of a near-field probe and circuit board characteristics, and a test result; and an IC reaching signal level estimation unit configured to estimate a signal level reaching a terminal of an evaluation target IC. The immunity evaluation device receives board design information, information of the near-field probe, and test waveform instruction information of a signal applied to the near-field probe.
    Type: Application
    Filed: November 18, 2021
    Publication date: August 25, 2022
    Inventors: Isao HOUDA, Aya OHMAE, Umberto PAOLETTI
  • Patent number: 11348735
    Abstract: A high voltage filter includes an anode bus bar, a cathode bus bar, a first capacitive element connected between the anode bus bar and a ground connector connected to a ground, a second capacitive element connected between the cathode bus bar and the ground connector, and a third capacitive element connected between the anode bus bar and the cathode bus bar. An anode terminal of the first capacitive element and a cathode terminal of the third capacitive element are arranged adjacent to each other, and a cathode terminal of the second capacitive element and an anode terminal of the third capacitive element are arranged adjacent to each other.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: May 31, 2022
    Assignee: Hitachi Astemo, Ltd.
    Inventors: Isao Houda, Aya Ohmae, Hiroki Funato, Yusaku Katsube, Ayumu Hatanaka
  • Publication number: 20210319956
    Abstract: A high voltage filter includes an anode bus bar, a cathode bus bar, a first capacitive element connected between the anode bus bar and a ground connector connected to a ground, a second capacitive element connected between the cathode bus bar and the ground connector, and a third capacitive element connected between the anode bus bar and the cathode bus bar. An anode terminal of the first capacitive element and a cathode terminal of the third capacitive element are arranged adjacent to each other, and a cathode terminal of the second capacitive element and an anode terminal of the third capacitive element are arranged adjacent to each other.
    Type: Application
    Filed: July 10, 2019
    Publication date: October 14, 2021
    Inventors: Isao HOUDA, Aya OHMAE, Hiroki FUNATO, Yusaku KATSUBE, Ayumu HATANAKA
  • Patent number: 10160334
    Abstract: Provided is a power conversion device capable of selectively suppressing harmonic noise in a frequency band and a machine equipped with the power conversion device. The power conversion device includes a switching element (13), a switching signal generation unit (23, 24) for generating a switching control signal for controlling the turning on/off of the switching element (13), and a control unit (18), and is characterized in that the switching control signal generation unit (23, 24) generates the switching control signal including a combination of a pair of symmetrical pulse waveforms having on and off periods that are interchanged with respect to a repeated cycle.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: December 25, 2018
    Assignee: Hitachi, Ltd.
    Inventors: Isao Houda, Masayoshi Takahashi, Hiroki Funato, Hitoshi Akiyama
  • Publication number: 20170015207
    Abstract: Provided is a power conversion device capable of selectively suppressing harmonic noise in a frequency band and a machine equipped with the power conversion device. The power conversion device includes a switching element (13), a switching signal generation unit (23, 24) for generating a switching control signal for controlling the turning on/off of the switching element (13), and a control unit (18), and is characterized in that the switching control signal generation unit (23, 24) generates the switching control signal including a combination of a pair of symmetrical pulse waveforms having on and off periods that are interchanged with respect to a repeated cycle.
    Type: Application
    Filed: December 8, 2014
    Publication date: January 19, 2017
    Inventors: Isao HOUDA, Masayoshi TAKAHASHI, Hiroki FUNATO, Hitoshi AKIYAMA
  • Publication number: 20040244048
    Abstract: A channel frequency allocation pattern deciding method, which is capable of quickly determining the channel frequency allocation pattern in the process of channel scanning in the cable TV system in the United States, is employed in a digital broadcast receiving apparatus. In the cable TV system, STD, IRC and HRC are used as channel frequency allocation patterns and these channel frequency allocation patterns must be discriminated. Digital channels are generally arranged at frequencies of 550 MHz or higher. Therefore, in the case of executing automatic channel scanning, automatic channel scanning is started at a channel of 550 MHz or higher, thus enabling quick discrimination of the channel frequency allocation patterns and significant reduction in the time required for the entire automatic channel scanning process.
    Type: Application
    Filed: September 25, 2003
    Publication date: December 2, 2004
    Inventors: Kenji Wada, Hitoshi Akiyama, Isao Houda