Abstract: A solid state imaging device according to an aspect of the present invention includes: a pixel array (21) including pixel units arranged in rows and columns; a vertical shift register (26) which selects one of the rows of the pixel array (21); a column amplifier unit (22) including column amplifiers each of which is provided for a corresponding one of the columns and amplifies a column signal provided from the pixel unit included in the selected row; and a limiting circuit which limits an output voltage of the column amplifier to no more than a predetermined voltage that can be changed, wherein the limiting circuit changes the predetermined voltage according to switching between a normal mode and a high-sensitivity mode.

Abstract: A counter circuit includes counting stages of n bits where n is a natural number. The counter circuit also includes a logic decoding circuit for determining the inputs of the counting stages, a logic circuit for adjusting the number of simultaneous changes so that the number of simultaneous changes of the logic decoding circuit can be made uniform, and a logic circuit for adjusting the load capacitance of the counting stages so that the load capacitance can be made uniform. The counter circuit may also include a test logic circuit for creating a test wave form on the basis of the outputs from the logic circuits for adjusting the number of simultaneous changes and the logic circuits for adjusting the load capacitance. Accordingly, it is possible to detect a failure of the logic circuits for adjusting the number of simultaneous changes and the logic circuits for adjusting the load capacitance which does not effect the counting output.

Abstract: A counter circuit which incurs a uniform number of logic changes whether the clock signal is rising or falling is used in both a first counter circuit for measuring the reference signal for horizontal scanning period and a second counter circuit for measuring signals in the vertical blanking period. Since the number of logic changes of the flip-flops with respect to the clock signal is uniform, a driving circuit for a solid-state image sensor is realized in which noise in the vertical blanking period does not appear in the video period even if by using 1H delay line.