Patents by Inventor Isao Isshiki

Isao Isshiki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8054605
    Abstract: A gate driver 28 performs a normal charging operation for a power MOSFET 14 by driving a charge pump 90 solely, when a low-level control signal S1 (ON signal) is received during a normal state. On the other hand, if a low-level control signal S1 (ON signal) is received during a load anomaly state, an urgent charge FET 92, as well as the charge pump 90, is turned on when a load current IL exceeds a second anomaly threshold current ILfc, so that a rapid charging operation is performed.
    Type: Grant
    Filed: February 20, 2007
    Date of Patent: November 8, 2011
    Assignees: Autonetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Seiji Takahashi, Masayuki Kato, Masahiko Furuichi, Isao Isshiki
  • Patent number: 7924542
    Abstract: A voltage-dividing circuit 60, which is formed of serially connected voltage-dividing resistors R1, R2, R3, is disposed between the source terminal S of a power MOSFET 15 and the ground. The divided voltage Va at a connecting point A is applied to one of the input terminals of a comparator 62, while the divided voltage Vb at a connecting point B is applied to one of the input terminals of a comparator 64. The other input terminals of the comparators 62, 64 are connected to the connecting line between an external terminal P4, to which an external resistor 12 is connected, and an FET 30.
    Type: Grant
    Filed: May 25, 2006
    Date of Patent: April 12, 2011
    Assignees: Autonetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Seiji Takahashi, Masayuki Kato, Masahiko Furuichi, Isao Isshiki
  • Patent number: 7701686
    Abstract: In a power supply controller 10 having a self-protective mechanism for performing, intermittently or periodically, a forced ON-OFF operation which causes a power MOSFET 15 to perform an automatically restorable primary disconnecting operation and a restoring operation when an overcurrent anomaly or an short-circuiting anomaly is detected, an automatically unrestorable secondary disconnecting operation is performed when the accumulated amount of the duration of the forced ON-OFF operation reaches an accumulation threshold.
    Type: Grant
    Filed: November 30, 2005
    Date of Patent: April 20, 2010
    Assignees: Autonetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Masayuki Kato, Isao Isshiki, Seiji Takahashi, Masahiko Furuichi
  • Patent number: 7639055
    Abstract: After an output signal S4 is level-inverted, first and second shorting FETs 55, 56 as a level-inversion inhibiting circuit inhibit level-inversion so that the signal is maintained to the inverted state. Thereafter the inhibition of level-inversion is released, when the signal is subsequently level-inverted at a proper time according to a desired duty ratio of a PWM signal S1. Thus chattering can be prevented and thereby a PWM signal S1 of a stable duty ratio can be generated, even if the level of a reference signal S3 fluctuates due to a noise or the like during vehicle acceleration, for example.
    Type: Grant
    Filed: October 17, 2006
    Date of Patent: December 29, 2009
    Assignees: Autonetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Masayuki Kato, Seiji Takahashi, Masahiko Furuichi, Isao Isshiki
  • Patent number: 7545127
    Abstract: A parallel circuit 27 of a frequency control circuit 11 is provided as an external circuit. Thereby, the charging time t1 depends on the characteristics of the circuit elements, which are provided in the package of a semiconductor device 70 and therefore subject to manufacturing variations of the semiconductor device 70. The discharging time t2 depends on the parallel circuit 27, which is provided external to the semiconductor device 70 and therefore can be selected to have appropriate characteristics after the semiconductor device 70 has been manufactured. The circuit constants of circuits are set so that the discharging time t2 that depends on the device characteristics of the external parallel circuit 27 is longer than the charging time t1 that depends on the device characteristics of the internal circuits of the semiconductor device 70.
    Type: Grant
    Filed: October 18, 2006
    Date of Patent: June 9, 2009
    Assignees: Autonetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Seiji Takahashi, Masayuki Kato, Masahiko Furuichi, Isao Isshiki
  • Publication number: 20090128106
    Abstract: A voltage-dividing circuit 60, which is formed of serially connected voltage-dividing resistors R1, R2, R3, is disposed between the source terminal S of a power MOSFET 15 and the ground. The divided voltage Va at a connecting point A is applied to one of the input terminals of a comparator 62, while the divided voltage Vb at a connecting point B is applied to one of the input terminals of a comparator 64. The other input terminals of the comparators 62, 64 are connected to the connecting line between an external terminal P4, to which an external resistor 12 is connected, and an FET 30.
    Type: Application
    Filed: May 25, 2006
    Publication date: May 21, 2009
    Applicants: Autonetworks Technologies, Ltd., Sumitomo Wiring Systems, Sumitomo Electric Industries, Ltd.
    Inventors: Seiji Takahashi, Masayuki Kato, Masahiko Furuichi, Isao Isshiki
  • Publication number: 20090108894
    Abstract: After an output signal S4 is level-inverted, first and second shorting FETs 55, 56 as a level-inversion inhibiting circuit inhibit level-inversion so that the signal is maintained to the inverted state. Thereafter the inhibition of level-inversion is released, when the signal is subsequently level-inverted at a proper time according to a desired duty ratio of a PWM signal S1. Thus chattering can be prevented and thereby a PWM signal S1 of a stable duty ratio can be generated, even if the level of a reference signal S3 fluctuates due to a noise or the like during vehicle acceleration, for example.
    Type: Application
    Filed: October 17, 2006
    Publication date: April 30, 2009
    Applicants: Autonetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Masayuki Kato, Seiji Takahashi, Masahiko Furuichi, Isao Isshiki
  • Publication number: 20090052096
    Abstract: A gate driver 28 performs a normal charging operation for a power MOSFET 14 by driving a charge pump 90 solely, when a low-level control signal S1 (ON signal) is received during a normal state. On the other hand, if a low-level control signal S1 (ON signal) is received during a load anomaly state, an urgent charge FET 92, as well as the charge pump 90, is turned on when a load current IL exceeds a second anomaly threshold current ILfc, so that a rapid charging operation is performed.
    Type: Application
    Filed: February 20, 2007
    Publication date: February 26, 2009
    Inventors: Seiji Takahashi, Masayuki Kato, Masahiko Furuichi, Isao Isshiki
  • Publication number: 20080258787
    Abstract: A parallel circuit 27 of a frequency control circuit 11 is provided as an external circuit. Thereby, the charging time t1 depends on the characteristics of the circuit elements, which are provided in the package of a semiconductor device 70 and therefore subject to manufacturing variations of the semiconductor device 70. The discharging time t2 depends on the parallel circuit 27, which is provided external to the semiconductor device 70 and therefore can be selected to have appropriate characteristics after the semiconductor device 70 has been manufactured. The circuit constants of circuits are set so that the discharging time t2 that depends on the device characteristics of the external parallel circuit 27 is longer than the charging time t1 that depends on the device characteristics of the internal circuits of the semiconductor device 70.
    Type: Application
    Filed: October 18, 2006
    Publication date: October 23, 2008
    Applicants: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Seiji Takahashi, Masayuki Kato, Masahiko Furuichi, Isao Isshiki
  • Publication number: 20080002325
    Abstract: In a power supply controller 10 having a self-protective mechanism for performing, intermittently or periodically, a forced ON-OFF operation which causes a power MOSFEET 15 to perform an automatically restorable primary disconnecting operation and a restoring operation when an overcurrent anomaly or an short-circuiting anomaly is detected, an automatically unrestorable secondary disconnecting operation is performed when the accumulated amount of the duration of the forced ON-OFF operation reaches an accumulation threshold.
    Type: Application
    Filed: November 30, 2005
    Publication date: January 3, 2008
    Applicants: Autonetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Masayuki Kato, Isao Isshiki, Seiji Takahashi, Masahiko Furuichi
  • Patent number: 7167377
    Abstract: A circuit-constituting unit forming a distribution circuit or the like in a vehicle. The circuit-constituting unit includes a plurality of bus bars for constituting a power circuit; a semiconductor switching device provided in the power circuit; and a control circuit board. The bus bars are bonded to a surface of the control circuit board such that the bus bars are arranged to be generally coplanar with each other. The semiconductor switching device is mounted on both of the corresponding bus bars and the control circuit board. An opening may be formed through the control circuit board. In this case, one of terminals of the semiconductor switching device may be connected to a surface of the control circuit board facing away from the surface to which the bus bars are bonded. The other terminals may be connected respectively to the bus bar through the opening.
    Type: Grant
    Filed: November 25, 2002
    Date of Patent: January 23, 2007
    Assignees: Sumitoo Wiring Systems, Ltd., Autonetworks Technologies, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Takahiro Onizuka, Isao Isshiki, Ryuji Nakanishi, Kouichi Takagi, Tou Chin, Shigeki Yamane
  • Patent number: 7075356
    Abstract: According to the charge pump circuit, a constant current charging and discharging circuit using follower circuits is interposed at current paths in charging and discharging a capacitor for stepping up. Transistors of the follower circuits are alternately made ON in accordance with a clock signal inputted from a signal input portion for switching to connect the capacitor for stepping up and restricting a current in cooperation with resistors or the like.
    Type: Grant
    Filed: February 13, 2004
    Date of Patent: July 11, 2006
    Assignees: Autonetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Shuji Mayama, Isao Isshiki
  • Patent number: 7046073
    Abstract: A load drive circuit includes a plurality of control sections for drive controlling of a drive switching element while protecting the drive switching element from a predetermined abnormality status, and a current blocking switching element being provided in at least any of a path between the control sections and a power source and a path between the control sections and a ground. When an input to an input circuit is OFF, a current flowing to a gate drive circuit for on/off driving of the drive switching element becomes an OFF state, the driving switching element becomes an OFF state, and the input circuit causes each current blocking switching element to be an OFF state to block dark current.
    Type: Grant
    Filed: February 12, 2004
    Date of Patent: May 16, 2006
    Assignees: Autonetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Shuji Mayama, Isao Isshiki
  • Patent number: 7031129
    Abstract: A protection circuit, to be provided for a circuit arrangement having an inductive load and an FET as an N-channel MOS transistor provided upstream of the load with respect to a flow of power current, the FET controlling an energization state of the load, the protection circuit includes a first connection changer interposed on a connection line between a gate of the FET and a gate drive voltage supply source, the first connection changer changing a connection state between a first connection state in which the gate is connected to the gate drive voltage supply and a second connection state in which the gate is connected to a ground.
    Type: Grant
    Filed: February 13, 2004
    Date of Patent: April 18, 2006
    Assignees: Autonetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Shuji Mayama, Isao Isshiki
  • Publication number: 20040227564
    Abstract: According to the charge pump circuit, a constant current charging and discharging circuit using follower circuits is interposed at current paths in charging and discharging a capacitor for stepping up. Transistors of the follower circuits are alternately made ON in accordance with a clock signal inputted from a signal input portion for switching to connect the capacitor for stepping up and restricting a current in cooperation with resistors or the like.
    Type: Application
    Filed: February 13, 2004
    Publication date: November 18, 2004
    Applicants: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Shuji Mayama, Isao Isshiki
  • Publication number: 20040228057
    Abstract: An overcurrent limit circuit including: a main function part which switches a drive current for a predetermined load between ON and OFF by an ON/OFF operation of a power-MOS-FET used as a drive switch, and which drives the power-MOS-FET and protects overcurrent; and a shunt-detection part which divides electric current applied to the drive switch from a power source side and detects the overcurrent, wherein the main function part, in case that the voltage between a drain of the power-MOS-FET and a source thereof is at least less than a predetermined threshold, has a function of limiting the electric current flowing in the power-MOS-FET on the basis of the overcurrent detected by the shunt-detection part.
    Type: Application
    Filed: February 12, 2004
    Publication date: November 18, 2004
    Applicants: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Shuji Mayama, Isao Isshiki
  • Publication number: 20040228058
    Abstract: A load drive circuit includes a plurality of control sections for drive controlling of a drive switching element while protecting the drive switching element from a predetermined abnormality status, and a current blocking switching element being provided in at least any of a path between the control sections and a power source and a path between the control sections and a ground. When an input to an input circuit is OFF, a current flowing to a gate drive circuit for on/off driving of the drive switching element becomes an OFF state, the driving switching element becomes an OFF state, and the input circuit causes each current blocking switching element to be an OFF state to block dark current.
    Type: Application
    Filed: February 12, 2004
    Publication date: November 18, 2004
    Applicants: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Shuji Mayama, Isao Isshiki
  • Publication number: 20040228059
    Abstract: A protection circuit, to be provided for a circuit arrangement having an inductive load and an FET as an N-channel MOS transistor provided upstream of the load with respect to a flow of power current, the FET controlling an energization state of the load, the protection circuit includes a first connection changer interposed on a connection line between a gate of the FET and a gate drive voltage supply source, the first connection changer changing a connection state between a first connection state in which the gate is connected to the gate drive voltage supply and a second connection state in which the gate is connected to a ground.
    Type: Application
    Filed: February 13, 2004
    Publication date: November 18, 2004
    Applicants: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Shuji Mayama, Isao Isshiki
  • Patent number: 6769637
    Abstract: Electromagnetic coil parts 25 and wiring 26 for connection to the electromagnetic coil parts 25 are installed inside injector electric block body 20 in which injector main body housing holes 21h are made in accordance with injector mounting holes Eh of the engine body E side, and injector main bodies 30 having valve parts 35 are inserted into the injector main body housing holes 21h, whereby the valve parts 35 are driven to open and close by means of exciting and non-exciting operation of the electromagnetic coil parts 25. Further, an ignition coil device module is provided with ignition coil devices 102 provided corresponding to a plurality of combustion chambers of an engine, respectively, wherein connection surface base portions at which connecting terminals are exposed are provided on one-side surface of each ignition coil device 102.
    Type: Grant
    Filed: November 28, 2001
    Date of Patent: August 3, 2004
    Assignees: Autonetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Kazushige Nakamura, Isao Isshiki, Takao Nozaki, Fumiyoshi Tanigawa
  • Publication number: 20040141292
    Abstract: In the power distributor using a semiconductor switching element, input terminals 10I and 10L, output terminals 12A-12J, connected to the element, and more preferably, the board terminals 30 and 32, are structured by a metallic plate, and arranged on the same plane perpendicular to the plate thickness. The metallic plate can be integrated by the resin mold, thereby the structure can be greatly simplified. The metallic plate can be produced by a greatly simple method by which, after the punching out of the metallic plate and the molding of the resin mold, a predetermined portion of the metallic plate is cut and the semiconductor switching element is mounted, and it can contribute to also the reduction of the cost.
    Type: Application
    Filed: January 6, 2004
    Publication date: July 22, 2004
    Applicants: Autonetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Takahiro Onizuka, Isao Isshiki, Shigeki Yamane