Abstract: In an image display device equipped with a panel having first and second electrodes, a field period is divided into a plurality of sub-field periods that each have a predetermined luminance weight, and a gray-scale image for is displayed by (a) writing sub-field image data of each sub-field period obtained by dividing input image data of the field period into the plurality of sub-field periods, into the panel through the first and second electrodes, and (b) sustaining an illumination state of ON or OFF in each cell for each sub-field period using luminance equivalent to a luminance weight of each sub-field period. The image display device includes an image changing unit for changing a part of sub-field image data of a predetermined sub-field period, so that a total number of charges and discharges performed on the first electrode when writing the sub-field image data becomes smaller.

Abstract: An image display apparatus which displays images, suppressing the occurrence of the moving image false edge. The image display apparatus selects a signal level among a plurality of signal levels in accordance with a motion amount of an input image signal, where each signal level is expressed by an arbitrary combination of 0, W1, W2, . . . and WN and luminance weights W1, W2, . . . and WN are assigned to subfields.

Abstract: An image display apparatus is provided for reducing occurrences of moving image false-edges by preventing profound changes in “on”/“off” subfield distribution, and for displaying a sharp image that does not appear blurred. This is achieved by effectively dividing one TV field and by displaying a gray level of an input image signal using an “on”/“off” subfield combination, out of possible “on”/“off” subfield combinations for displaying the gray level, in which a number of subfields with large luminance weightings that are “on” is minimized.

Abstract: A plasma display having a quartet type pixel structure provides a high grade and excellent picture quality picture and maintains good white balance and excellent intensity levels. The plasma display comprises a reference circuit .phi. for outputting a control signal based on the least significant bit of a digitized green video signal and a timing signal and an arithmetic circuit 8 for performing an arithmetic operation on the output of the reference circuit. As a result of this arrangement, the least significant bit information, that was lost by halving the green signal value to maintain the white balance is incorporated in the halved green signal based on a timing signal, thereby realizing 256 intensity levels without degrading the halftone in the video picture.

Abstract: An image receiver control apparatus for performing clamp signal processing includes an analog clamper (30) for clamping an input signal on a predetermined DC level, an A/D converter (31) for A/C-converting an output from the analog clamper (30) with a predetermined sample period of time, a timing signal generator (33), a central processing unit (CPU) (38), a data selector (34) for selecting one of a data signal output from the A/D converter (31) and a data signal on a data bus (382) connected to the CPU (38) to supply the selected data signal to the RAM (35), and an address selector (37) for selecting one of an address from the counter (36) and an address on an address bus (381) connected to the CPU (38) to supply the selected address to the RAM (35).

Abstract: A clamp system for television signal comprises a first clamp device for clamping to a clamp control voltage supplied from an external source by a horizontal clamp pulse and a second clamp device for controlling the DC potential of the television signal by adding the externally-supplied control voltage to an input television signal. The first clamp device is used during the period requiring an early clamp start, and the second clamp device is operated under normal conditions.

Abstract: An automatic gain control system for controlling a gain of an A/D converter automatically by controlling reference voltages of said A/D converter at the time of analog-to-digital conversion of a signal which signal being clamped by a clamp circuit to a clamp level which is set to a center level before entering said A/D converter, comprising a clamp level control circuit for detecting the clamp level from an output of said A/D converter to control the clamp level; a first A/D converter for digital-to-analog converting an output of said clamp level control circuit; an automatic clamp level control system.