Patents by Inventor Isao Makabe
Isao Makabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240290825Abstract: A semiconductor device includes a barrier layer having an upper surface with a nitrogen polarity, a channel layer having an upper surface with a nitrogen polarity, provided on the barrier layer, a silicon nitride film provided on the channel layer, a dielectric film provided on the silicon nitride film, and a gate electrode provided on the dielectric film. A relative dielectric constant of the dielectric film is higher than a relative dielectric constant of the silicon nitride film.Type: ApplicationFiled: February 21, 2024Publication date: August 29, 2024Inventors: Akira MUKAI, Masaya OKADA, Isao MAKABE, Akihiro HAYASAKA
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Patent number: 11935744Abstract: A method for manufacturing a nitride semiconductor device includes the steps of growing a GaN channel layer on an SiC substrate using a vertical MOCVD furnace set at a first temperature using H2 as a carrier gas, and TMG and NH3 as raw materials, holding the SiC substrate having the grown GaN channel layer in the MOCVD furnace set at a second temperature higher than the first temperature using H2 as a carrier gas, the MOCVD furnace being supplied with NH3, and growing an InAlN layer on the GaN channel layer using the MOCVD furnace set at a third temperature lower than the first temperature using N2 as a carrier gas, and TMI, TMA, and NH3 as raw materials.Type: GrantFiled: December 16, 2019Date of Patent: March 19, 2024Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Isao Makabe, Ken Nakata
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Publication number: 20230036388Abstract: A method of manufacturing a semiconductor device includes forming a first nitride semiconductor layer containing Ga on a substrate; forming a first layer on the first nitride semiconductor layer; forming a second layer on the first layer; forming an opening in which the first nitride semiconductor layer is exposed in the second layer and the first layer; forming a second nitride semiconductor layer of a first conductivity type on a surface, exposed in the opening, of the first nitride semiconductor layer; removing the second layer using an acidic solution; and after removing the second layer, forming an electrode on the second nitride semiconductor layer. A first etching rate of the first layer for the acidic solution is lower than a second etching rate of the second layer for the acidic solution.Type: ApplicationFiled: June 7, 2022Publication date: February 2, 2023Applicant: Sumitomo Electric Industries, Ltd.Inventor: Isao MAKABE
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Publication number: 20210398801Abstract: A method for manufacturing a nitride semiconductor device includes the steps of growing a GaN channel layer on an SiC substrate using a vertical MOCVD furnace set at a first temperature using H2 as a carrier gas, and TMG and NH3 as raw materials, holding the SiC substrate having the grown GaN channel layer in the MOCVD furnace set at a second temperature higher than the first temperature using H2 as a carrier gas, the MOCVD furnace being supplied with NH3, and growing an InAlN layer on the GaN channel layer using the MOCVD furnace set at a third temperature lower than the first temperature using N2 as a carrier gas, and TMI, TMA, and NH3 as raw materials.Type: ApplicationFiled: December 16, 2019Publication date: December 23, 2021Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Isao MAKABE, Ken NAKATA
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Patent number: 10622470Abstract: A process of forming a semiconductor device primarily made of nitride semiconductor materials is disclosed. The process includes steps of: (a) growing a semiconductor stack including a channel layer and a barrier layer sequentially on a substrate, where the channel layer is made of gallium nitride (GaN); (b) patterning a mask on the barrier layer; (c) etching a portion of the barrier layer and a portion of the channel layer with the mask to form a recess in the semiconductor stack; and (d) growing a contact layer selectively within the recess with nitrogen (N2) used as a carrier gas at a maximum temperature of 1000° C.Type: GrantFiled: August 6, 2018Date of Patent: April 14, 2020Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventor: Isao Makabe
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Patent number: 10505013Abstract: A process of forming a high electron mobility transistor (HEMT) with a reverse arrangement for the barrier layer and the channel layer thereof is disclosed. The process includes steps of epitaxially growing an oxide layer containing zinc (Zn) on a substrate where the oxide layer shows an O-polar surface; epitaxially growing a semiconductor stack made of nitride semiconductor materials on the oxide layer where the semiconductor stack includes a nitride semiconductor layer, a barrier layer and a channel layer on the oxide layer in this order; attaching a temporal substrate to the semiconductor stack; removing the substrate and the oxide layer from the semiconductor stack; attaching a support substrate to the nitride semiconductor layer; and removing the temporal substrate from the semiconductor stack.Type: GrantFiled: July 20, 2018Date of Patent: December 10, 2019Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventor: Isao Makabe
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Publication number: 20190043978Abstract: A process of forming a semiconductor device primarily made of nitride semiconductor materials is disclosed. The process comprises steps of: (a) growing a semiconductor stack including a channel layer and a barrier layer sequentially on a substrate, where the channel layer being made of gallium nitride (GaN) on a substrate; (b) patterning a mask on the barrier layer; (c) etching a portion of the barrier layer and a portion of the channel layer using the mask to form a recess in the semiconductor stack; and (d) growing a contact layer selectively within the recess using nitrogen (N2) as a carrier gas at a temperature of 1000° C. at highest.Type: ApplicationFiled: August 6, 2018Publication date: February 7, 2019Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventor: Isao MAKABE
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Publication number: 20190027577Abstract: A process of forming a high electro mobility transistor (HEMT) with a reveres arrangement for the barrier layer and the channel layer thereof is disclosed. The process includes steps of epitaxially growing an oxide layer containing zinc (Zn) on a substrate where the oxide layer showing an O-polar surface; epitaxially growing a semiconductor stack made of nitride semiconductor materials on the oxide layer where the semiconductor stack includes a nitride semiconductor layer, a barrier layer and a channel layer on the oxide layer in this order; attaching a temporal substrate to the semiconductor stack; removing the substrate and the oxide layer from the semiconductor stack; attaching a support substrate to the nitride semiconductor layer; and removing the temporal substrate from the semiconductor stack.Type: ApplicationFiled: July 20, 2018Publication date: January 24, 2019Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventor: Isao Makabe
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Patent number: 10038086Abstract: A process of forming a High Electron Mobility Transistor (HEMT) made of nitride semiconductor materials is disclosed. The process sequentially grows a buffer layer, a n-type layer doped with n-type dopants, and a channel layer by a metal organic chemical vapor deposition (MOCVD) technique. A feature of the process is to supply only an n-type dopant gas before the growth of the n-type layer but after the growth of the buffer layer.Type: GrantFiled: March 15, 2017Date of Patent: July 31, 2018Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Ken Nakata, Tsuyoshi Kouchi, Isao Makabe, Keiichi Yui
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Publication number: 20180158926Abstract: A process of forming a nitride semiconductor is disclosed. The process includes steps of (a) growing an aluminum gallium nitride (GaN) as a channel layer, and (b) growing an indium aluminum gallium nitride (InAlGaN) as a barrier layer. The InAlGaN layer is grown at a temperature lower than a growth temperature for the GaN, and has an indium (In) composition less than 14% but preferably greater than 10%. The InAlGaN is substantially lattice-matched with the GaN.Type: ApplicationFiled: December 4, 2017Publication date: June 7, 2018Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Ken Nakata, Isao Makabe
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Publication number: 20180053648Abstract: A method of manufacturing a semiconductor device according to an embodiment of the present invention includes steps of forming an AlN layer on a SiC substrate under conditions of a growth temperature of 1100° C. or lower, growth pressure of 100 torr or less and a V/III ratio of source gasses of 500 or less, forming a channel layer made of a nitride semiconductor, forming an electron supply layer, and forming gate, source, and drain electrodes.Type: ApplicationFiled: October 13, 2017Publication date: February 22, 2018Inventors: Ken Nakata, Keiichi Yui, Hiroyuki Ichikawa, Isao Makabe, Tsuyoshi Kouchi
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Patent number: 9355843Abstract: A method of manufacturing a semiconductor device according to one aspect of the present invention includes a step of forming a first layer of InAlN, a step of forming a second layer of InAlGaN on the first layer under a growth temperature higher than that of the first layer, and a step of forming a third layer of GaN, AlGaN or InGaN under a growth temperature higher than that of the first layer.Type: GrantFiled: July 27, 2015Date of Patent: May 31, 2016Assignee: Sumitomo Electric Industries, Ltd.Inventors: Keiichi Yui, Ken Nakata, Tsuyoshi Kouchi, Isao Makabe
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Publication number: 20160149024Abstract: An electron device formed by primarily nitrides semiconductor materials and a method to form the electron device are disclosed. The electron device includes, on the SiC substrate, a buffer layer of AlN, a channel layer of GaN, and an electron supplying layer of AlGaN. The AlGaN layer has the oxygen concentration higher than the carbon concentration in the whole thereof. The AlGaN layer is grown on the channel layer under conditions of: a ratio of the flow rate of the ammonia gas against the flow rate of the gases for Al and Ga is 5000 to 20000; and/or the growth, rate of the AlGaN layer is slower than 0.2 nm/sec.Type: ApplicationFiled: November 19, 2015Publication date: May 26, 2016Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventor: Isao MAKABE
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Publication number: 20160111274Abstract: A method for producing a nitride semiconductor device is disclosed. The method includes steps of: forming a channel layer, an InAlN doped layer sequentially on the substrate, raising a temperature of the substrate as supplying a gas source containing In, and/or another gas source containing Al, and growing GaN layer on the InAlN doped. Or, the method grows the channel layer, the InAlN layer, and another GaN layer sequentially on the substrate, raising the temperature of the substrate, and growing the GaN layer. These methods suppress the sublimation of InN from the InAlN layer.Type: ApplicationFiled: December 30, 2015Publication date: April 21, 2016Inventors: Keiichi Yui, Ken Nakata, Isao Makabe, Tsuyoshi Kouchi
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Publication number: 20150332915Abstract: A method of manufacturing a semiconductor device according to one aspect of the present invention includes a step of forming a first layer of InAlN, a step of forming a second layer of InAlGaN on the first layer under a growth temperature higher than that of the first layer, and a step of forming a third layer of GaN, AlGaN or InGaN under a growth temperature higher than that of the first layer.Type: ApplicationFiled: July 27, 2015Publication date: November 19, 2015Inventors: Keiichi Yui, Ken Nakata, Tsuyoshi Kouchi, Isao Makabe
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Publication number: 20150279942Abstract: A process to obtain a nitride transistor containing a gallium nitride (GaN) is disclosed. The process first grows an AlN layer on a substrate, then crown the GaN layer cc the AlN layer. Between the growth of the AlN layer and the GaN layer, the process leaves the AlN layer grown art the substrate in a temperature higher than the growth temperature of the AlN layer for a preset period. This heat treatment of the AlN layer sublimates impurities accumulated on the surface of the AlN layer and enhances the crystal quality of the GaN layer grown thereon.Type: ApplicationFiled: March 17, 2015Publication date: October 1, 2015Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Keiichi YUI, Ken Nakata, Isao Makabe, Tsuyoshi Kouchi
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Publication number: 20150279658Abstract: A method to produce a nitride semiconductor device is disclosed, The method includes a step to grow sequentially, on a substrate, an AlN layer, a AlGaN layer with the Al composition not less than 2.5% but not greater than 9%, a GaN layer with a thickness not less than 250 nm but not greater than 1400 nm. A feature of the process is that, after the growth of the AlGaN layer but before the growth of the GaN layer, at least the source gases for the group III elements are interrupted to be supplied for a period of not less than 80 seconds but not longer than 220 seconds.Type: ApplicationFiled: March 24, 2015Publication date: October 1, 2015Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Keiichi YUI, Ken Nakata, Isao Makabe, Tsuyoshi KOUCHI
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Patent number: 9123534Abstract: A method of manufacturing a semiconductor device according to one aspect of the present invention includes a step of forming a first layer of InAlN, a step of forming a second layer of InAlGaN on the first layer under a growth temperature higher than that of the first layer, and a step of forming a third layer of GaN, AlGaN or InGaN under a growth temperature higher than that of the first layer.Type: GrantFiled: June 5, 2014Date of Patent: September 1, 2015Assignee: Sumitomo Electric Industries, Ltd.Inventors: Keiichi Yui, Ken Nakata, Tsuyoshi Kouchi, Isao Makabe
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Patent number: 9029873Abstract: The semiconductor device includes a SiC substrate; an aluminum nitride layer provided on the substrate and having an island-shaped pattern consisting of plural islands: a channel layer provided on the AlN layer and comprising a nitride semiconductor; an electron supplying layer provided on the channel layer and having a band gap larger than that of the channel layer; and a gate, source and drain electrodes on the electron supply layer. The AlN layer has an area-averaged circularity Y/X of greater than 0.2. Y is a sum of values obtained by multiplying circularities of the plural islands by areas of the plural islands respectively, X is a sum of the areas of the plural islands. The circularity are calculated by a formula of (4?×area)/(length of periphery)2 where the area and the length of periphery are an area and a length of periphery of each island.Type: GrantFiled: March 5, 2014Date of Patent: May 12, 2015Assignee: Sumitomo Electric Industries, Ltd.Inventors: Ken Nakata, Keiichi Yui, Tsuyoshi Kouchi, Isao Makabe, Hiroyuki Ichikawa
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Patent number: 8993416Abstract: A method of manufacturing a semiconductor device includes growing a first GaN layer on a SiC substrate, and forming a second GaN layer on the first GaN layer, the second GaN layer being grown under such conditions that a ratio of a vertical growth rate to a horizontal growth rate is lower than that in the growth of the first GaN layer.Type: GrantFiled: July 29, 2011Date of Patent: March 31, 2015Assignee: Sumitomo Electric Industries, Ltd.Inventors: Keiichi Yui, Ken Nakata, Isao Makabe, Hiroyuki Ichikawa