Abstract: A CAN module receives a message from a CAN bus to store the same in a message box unit of a message box. A reception request signal is output from the message box unit to a DMAC/IF. The DMAC/IF outputs a 7-bit encoded address together with a transfer request signal. A DMAC accesses a selected message box unit of the CAN module and a memory based on the transfer request signal and the 7-bit encoded address to transfer the message stored in the selected message box unit to the memory.

Abstract: A CAN module receives a message from a CAN bus to store the same in a message box unit of a message box. A reception request signal is output from the message box unit to a DMAC/IF. The DMAC/IF outputs a 7-bit encoded address together with a transfer request signal. A DMAC accesses a selected message box unit of the CAN module and a memory based on the transfer request signal and the 7-bit encoded address to transfer the message stored in the selected message box unit to the memory.

Abstract: A CAN module receives a message from a CAN bus to store the same in a message box unit of a message box. A reception request signal is output from the message box unit to a DMAC/IF. The DMAC/IF outputs a 7-bit encoded address together with a transfer request signal. A DMAC accesses a selected message box unit of the CAN module and a memory based on the transfer request signal and the 7-bit encoded address to transfer the message stored in the selected message box unit to the memory.

Abstract: An address range of consecutive instructions stored in an instruction buffer is set in an address table. A determination unit determines whether an instruction address outputted from a CPU core falls within the address range set in the address table. A selector selectively outputs an instruction code stored in the instruction buffer and an instruction code stored in an instruction cache in accordance with a determination result of the determination unit. Therefore, in the case where the CPU core fetches an instruction stored in the instruction buffer, an access cycle is guaranteed and an operation of the instruction cache is stopped, thereby making it possible to improve power efficiency.

Abstract: A CAN module receives a message from a CAN bus to store the same in a message box unit of a message box. A reception request signal is output from the message box unit to a DMAC/IF. The DMAC/IF outputs a 7-bit encoded address together with a transfer request signal. A DMAC accesses a selected message box unit of the CAN module and a memory based on the transfer request signal and the 7-bit encoded address to transfer the message stored in the selected message box unit to the memory.

Abstract: A data processing device includes a memory system capable of a plurality of simultaneous accesses, a plurality of address generators each generating an address for accessing the memory system, an addressing register having a plurality of address registers, a data processing unit providing an operation process to the data read from the memory system, and a control unit controlling operations of the plurality of address generators and the data processing unit. The plurality of address generators can generate addresses from a common value in one address register to simultaneously read data designated by the generated addresses from the memory system.

Abstract: An address range of consecutive instructions stored in an instruction buffer is set in an address table. A determination unit determines whether an instruction address outputted from a CPU core falls within the address range set in the address table. A selector selectively outputs an instruction code stored in the instruction buffer and an instruction code stored in an instruction cache in accordance with a determination result of the determination unit. Therefore, in the case where the CPU core fetches an instruction stored in the instruction buffer, an access cycle is guaranteed and an operation of the instruction cache is stopped, thereby making it possible to improve power efficiency.

Abstract: In a processor, a plurality of instructions in a program are executed in parallel using a plurality of functional units within the processor. Determination of which functional unit is to be used to execute each instruction is made when the program is produced prior to execution. The processor has the priority as to access of the PSW among the plurality of functional units predetermined when the contents of a PSW (Program Status Word) storage register in the processor are to be accessed simultaneously by a plurality of instructions during parallel execution of a plurality of instructions. Execution control can be provided of a program that reliably avoids a PSW access a conflict by a plurality of instructions during parallel execution of a plurality of instructions using a plurality of functional units in the processor.

Abstract: A remote debugging apparatus that uses a development terminal coupled to an evaluation board with a plurality of processing modules including a processor in a master-slave configuration, includes: a setting module for pre-setting a breakpoint in a program executed in the evaluation board; and a registering module for registering a procedure in a database provided either on the evaluation board or on the development terminal. The procedure is performed for a memory on the evaluation board when the breakpoint is hit. The apparatus further includes; an execution-commencing module for starting the program in the evaluation board; and an execution-controlling module for referencing the database in response to a hit on the breakpoint, and controlling the processing module of the evaluation board to execute a procedure required to be done on the memory of the evaluation board.

Abstract: A microprocessor includes a program control unit controlling fetch of an instruction code, an instruction decode unit decoding the fetched instruction code, an address operation unit operating an address of a memory on the basis of the result of decoding by the instruction decode unit and a data operation unit executing data transfer between a control register and a work register and data transfer between the work register and an X memory in correspondence to a single push instruction. Therefore, data stored in the control register incapable of directly pushing data on the memory can be pushed with a single push instruction.

Abstract: When a decision circuit (217) incorporated in a control circuit (21) in an instruction decode unit (2) in a microprocessor (1) decides that an integer operation unit (4) can not execute a following sub instruction, the decision circuit (217) controls each of selectors (211, 214, and 215) and an exchange circuit (216) so that a memory access unit (3) that has already executed a preceding sub instruction can execute the following sub instruction.

Abstract: A data processing device includes a memory system capable of a plurality of simultaneous accesses, a plurality of address generators each generating an address for accessing the memory system, an addressing register having a plurality of address registers, a data processing unit providing an operation process to the data read from the memory system, and a control unit controlling operations of the plurality of address generators and the data processing unit. The plurality of address generators can generate addresses from a common value in one address register to simultaneously read data designated by the generated addresses from the memory system.

Abstract: A graphic display control apparatus which automatically scrolls display contents of a screen vertically, horizontally or diagonally by automatically updating the reading address corresponding to the amount of scrolling, when read-out areas for display information of one screen read out from a frame memory whose capacity allows a CPU to write display information larger than one screen, e.g., an animation background, a motorcar navigation map or the like therein are sequentially moved, thereby to lighten the burden of the CPU at the scrolling time.