Abstract: A semiconductor device capable of verifying whether or not correct acquirement of image data from a sensor has been successful is provided. A semiconductor device includes: a reception interface circuit receiving a plurality of packets including a plurality of line data, respectively, and outputting an image composite signal generated by linking a line synchronization signal with each of the plurality of line data; and a capture circuit provided at a subsequent stage of the reception interface circuit. The capture circuit includes: a line counter receiving, as its input, the line synchronization signal included in the image composite signal, and counting the number of times of the input of the line synchronization signal; and a comparator comparing a count value counted by the line counter with a preset expected value of the number of lines, and outputting an error signal if the count value and the expected value do not match each other.

Abstract: A semiconductor device or image processing system includes n interface circuit and a channel composite circuit. The interface circuit outputs a first packet including the line data of the k-th line included in the image data of the first channel, and then outputs a second packet including the line data of the k-th line included in the image data of the second channel. The channel combination circuit writes, to the memory, the line data of the k-th line included in the image data of the first channel to the first address area, and then writes the line data of the k-th line included in the image data of the second channel to the second address area that is consecutive to the first address area.

Abstract: A semiconductor device capable of shortening processing time of a neural network is provided. The memory stores a compressed weight parameter. A plurality of multiply accumulators perform a multiply-accumulation operation to a plurality of pixel data and a plurality of weight parameters. A decompressor restores the compressed weight parameter stored in the memory to a plurality of weight parameters. A memory for weight parameter stores the plurality of weight parameters restored by the decompressor. The DMA controller transfers the plurality of weight parameters from the memory to the memory for weight parameter via the decompressor. A sequence controller writes down the plurality of weight parameters stored in the memory for weight parameter to a weight parameter buffer at write timing.

Abstract: The semiconductor device includes an image signal processor, a scaler, and an ROI (Region of Interest) controller. The image signal processor executes image processing including demosaic processing and stores the image after the image processing in memory. The scaler reduces the capture image from the image sensor to generate a reduced entire image and causes the image signal processor to execute image processing on the reduced entire image. The ROI controller cuts out a partial region of the captured image from the image sensor to generate an ROI image and causes the image signal processor to execute image processing on the ROI image.

Abstract: A semiconductor device executes the processing of a neural network. The memory MEM1 holds a plurality of pixel values and j compressed weighting factors. The decompressor DCMP restores the j compressed weighting factors to the uncompressed k (k?j) weighting factors. The DMA controller DMAC1 reads the j compressed weighting factors from the memory MEM1 and transfers them to the decompressor DCMP. The n (n>k) accumulators in the accumulator unit ACCU multiply a plurality of pixel values and k uncompressed weighting factor to accumulate and add the multiplication results to the time series. A switch circuit SW1 provided between the decompressor DCMP and the accumulator unit ACCU transfers the k uncompressed weighting factors restored by the decompressor DCMP to n accumulators based on the correspondence represented by the identifier.

Abstract: A semiconductor device (100) according to an embodiment calculates the number of times of burst access for an address set (A) based on a result of a determination, for each of N addresses a1 to an (N is a natural number no less than two) included in the address set (A), whether or not the address and another address adjacent to that address in an accessing order can be accessed by the same burst access, and calculates an access time that will be taken for accessing the address set by the burst access.

Abstract: A semiconductor device (100) according to an embodiment calculates the number of times of burst access for an address set (A) based on a result of a determination, for each of N addresses a1 to an (N is a natural number no less than two) included in the address set (A), whether or not the address and another address adjacent to that address in an accessing order can be accessed by the same burst access, and calculates an access time that will be taken for accessing the address set by the burst access.

Abstract: Herein disclosed is a bit stream separating and merging system comprising a bit stream separating apparatus (1000) for inputting and transcoding an original bit stream A to separate into and generate a base bit stream B and one or more extended differential bit streams E*, each having a partial differential information segment between the original bit stream A and the base bit stream B, and a bit stream merging apparatus (2000) for inputting and merging the base bit stream B and the one or more extended differential bit streams E* to reconstruct the original bit stream A or a pseudo original bit stream B* approximately similar to the original bit stream A.

Abstract: Herein disclosed is a multiple-output bit stream separating apparatus for inputting an original MPEG-2 bit stream to separate into a plurality of transcoded MPEG-2 bit streams and a plurality of differential bit streams, and a multiple-output bit stream merging apparatus for inputting the transcoded MPEG-2 bit stream and the differential bit streams to reconstruct the original MPEG-2 bit stream. The bit rate of the transcoded MPEG-2 bit stream and the differential bit streams thus multiple times separated are much lower than that of the original MPEG-2 bit stream. This leads to the fact that the multiple-output bit stream separating apparatus and the multiple-input bit stream merging apparatus can promptly and reliably transmit and receive an original MPEG-2 bit stream having a large bit rate by transmitting and receiving a plurality of transcoded MPEG-2 bit streams and a plurality of differential bit streams in place of the original MPEG-2 bit stream.

Abstract: Herein disclosed is a multiple-output bit stream separating apparatus for inputting an original MPEG-2 bit stream to separate into a plurality of transcoded MPEG-2 bit streams and a plurality of differential bit streams, and a multiple-output bit stream merging apparatus for inputting the transcoded MPEG-2 bit stream and the differential bit streams to reconstruct the original MPEG-2 bit stream. The bit rate of the transcoded MPEG-2 bit stream and the differential bit streams thus multiple times separated are much lower than that of the original MPEG-2 bit stream. This leads to the fact that the multiple-output bit stream separating apparatus and the multiple-input bit stream merging apparatus can promptly and reliably transmit and receive an original MPEG-2 bit stream having a large bit rate by transmitting and receiving a plurality of transcoded MPEG-2 bit streams and a plurality of differential bit streams in place of the original MPEG-2 bit stream.

Abstract: Herein disclosed a bit stream separating apparatus for inputting and transcoding an original MPEG-2 bit stream, and separating the transcoded MPEG-2 bit stream to generate a transcoded MPEG-2 bit stream and a differential bit stream, which is a differential bit stream between the original MPEG-2 bit stream and the transcoded MPEG-2 bit stream, and a bit stream merging apparatus for inputting and merging the transcoded MPEG-2 bit stream and the differential bit stream to reconstruct the original MPEG-2 bit stream. The bit stream separating apparatus makes it possible for the bit stream merging apparatus to reconstruct the original, high quality, MPEG-2 bit stream from the transcoded MPEG-2 bit stream already received and the differential bit stream, thereby eliminating the effort and time to send the original MPEG-2 bit stream again.

Abstract: A coded signal separating apparatus, coded signal merging apparatus, coded signal separating and merging system, and methods thereof capable of performing scalable transmission of images are provided. There are provided a separating unit 1100, which is a separator separating means for separating a coded stream into a basic coded signal B having a smaller code amount than the coded stream and a plurality of extended coded signals E(m), which are used with the basic coded signal B to reconstruct an image, and a multiplexing unit 1600, which is a separator multiplexing means for optionally combining and multiplexing the basic coded signal B with the plurality of extended coded signals E(m) to generate a plurality of transmission coded signals St(1), to thereby generate and output separated streams St(1), which are multiplexed transmission coded signals.

Abstract: Herein disclosed is a multiple-output bit stream separating apparatus for inputting an original MPEG-2 bit stream to separate into a plurality of transcoded MPEG-2 bit streams and a plurality of differential bit streams, and a multiple-output bit stream merging apparatus for inputting the transcoded MPEG-2 bit stream and the differential bit streams to reconstruct the original MPEG-2 bit stream. The bit rate of the transcoded MPEG-2 bit stream and the differential bit streams thus multiple times separated are much lower than that of the original MPEG-2 bit stream. This leads to the fact that the multiple-output bit stream separating apparatus and the multiple-input bit stream merging apparatus can promptly and reliably transmit and receive an original MPEG-2 bit stream having a large bit rate by transmitting and receiving a plurality of transcoded MPEG-2 bit streams and a plurality of differential bit streams in place of the original MPEG-2 bit stream.

Abstract: Herein disclosed a bit stream separating apparatus for inputting and transcoding an original MPEG-2 bit stream, and separating the transcoded MPEG-2 bit stream to generate a transcoded MPEG-2 bit stream and a differential bit stream, which is a differential bit stream between the original MPEG-2 bit stream and the transcoded MPEG-2 bit stream, and a bit stream merging apparatus for inputting and merging the transcoded MPEG-2 bit stream and the differential bit stream to reconstruct the original MPEG-2 bit stream. The bit stream separating apparatus makes it possible for the bit stream merging apparatus to reconstruct the original, high quality, MPEG-2 bit stream from the transcoded MPEG-2 bit stream already received and the differential bit stream, thereby eliminating the effort and time to send the original MPEG-2 bit stream again.