Patents by Inventor Isao Nakamura

Isao Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110071955
    Abstract: A transportation schedule planning support system receives an order of one or more types of products which requires a use-by date control, and transports the products from one or more stock-carrying bases to one or more delivery destinations. In the system, a user previously registers a transportation route candidate from a stock-carrying base to each delivery destination adoptable as a solution, as a base group. A necessary use-by date for a product to be delivered next is determined based on an actual delivery to each delivery destination. The number of vehicles allocatable to a transportation at each base according to a vehicle type, and a vehicle type not used in each base group are added to a restriction condition. A mixed integer programming is applied using an expected obtainable profit obtained by delivering each product as an objective function.
    Type: Application
    Filed: March 18, 2010
    Publication date: March 24, 2011
    Inventors: Isao Nakamura, Jun Tateishi, Katsunari Ikezawa, Takeshi Kurata, Yasuhiro Nemoto, Shinichirou Hanawa
  • Publication number: 20100285310
    Abstract: A production method of producing a plastic film-inserted laminated glass comprising a first step for subjecting a plastic interlayer and a plastic film to a thermocompression bonding, a second step for placing another plastic interlayer on the plastic film that has been subjected to the thermocompression bonding at the first step, thereby to produce a laminated film, a third step for putting the laminated film produced at the second step between two curved glass plates thereby to produce a laminated body, a fourth step for applying the laminated body with pressure and heat by using an autoclave thereby to achieve bonding of entire construction of the laminated body and a fifth step for cutting and removing the laminated film that protrudes from edges of the curved glass plates.
    Type: Application
    Filed: December 16, 2008
    Publication date: November 11, 2010
    Applicant: Central Glass Company ,Limited
    Inventors: Kensuke Izutani, Atsushi Takamatsu, Masaaki Yonekura, Isao Nakamura
  • Publication number: 20100285280
    Abstract: According to the present invention, there is provided a plastic film-inserted laminated glass comprising an outdoor side glass plate, an interlayer, a plastic film, another interlayer and an indoor side glass plate which are laminated in this order, which is characterized in that the glass plates have a curved shape formed by bending, the plastic film includes an infrared reflecting film formed thereon and at least at one side of the laminated glass, an edge of the plastic film is placed apart from corresponding edges of the glass plates by a distance ranging from 5 mm to 200 m in a direction toward a central portion of the glass plates.
    Type: Application
    Filed: December 16, 2008
    Publication date: November 11, 2010
    Applicant: Central Glass Company, Limited
    Inventors: Masaaki Yonekura, Isao Nakamura, Kensuke Izutani, Atsushi Takamatsu
  • Patent number: 7764292
    Abstract: The present invention provides a three dimensional graphics processing apparatus for performing an anti-aliasing processing in an sufficient manner, without using the conventional area DDA, by using a line buffer as an area for storing display image data to reduce the required memory area, while the increase of the calculation time is restricted by performing calculation suitable for the polygon edge without degrading the precision of the calculation. In the three dimensional graphics processing apparatus, the coordinates of the intersection points between the polygon edge and the scanning lines are calculated from information on the starting vertex and the ending vertex of the polygon edge and information on the scanning lines. The calculation method is changed in accordance with the characteristics of the polygon edge. Further, a blending coefficient for the anti-aliasing process is obtained by calculating an area ratio of an internal region of the polygon occupied within a pixel.
    Type: Grant
    Filed: November 15, 2005
    Date of Patent: July 27, 2010
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hiroaki Fukui, Isao Nakamura
  • Publication number: 20100121911
    Abstract: Transfer control means (41) transfers part of held digital contents in an internal storage device (51) to a network storage device (57). List information presentation means (42) returns list information which makes the digital contents stored in the internal storage device (51) and the network storage device (57) as the held digital contents in response to a list presentation request for the held digital contents. Upon reception of a data transmission request, search means (43) searches where the held digital contents are currently stored. If the result of the search shows the network storage device (57), content data transmission processing means (44) allows the stream-delivery of the data from the network storage device (57) to a network player (56). There is provided a server device for media (40) capable of maintaining the convenience of playback in a network player, while properly dealing with the large total size of held digital contents.
    Type: Application
    Filed: March 2, 2007
    Publication date: May 13, 2010
    Inventors: Satoru Sekiguchi, Yoshio Sonoda, Isao Nakamura, Masamichi Furukawa, Yoshihisa Mashita, Tomoaki Yoshida, Masahito Watanabe
  • Publication number: 20090292384
    Abstract: A manufacturing instruction evaluation support system includes a data reading part that reads a manufacturing instruction parameter group and manufacturing performance data corresponding thereto, a parameter sorting part that calculates a risk rate for each manufacturing instruction parameter configuring the manufacturing instruction parameter group and an average value of risk rates among the manufacturing instruction parameters to identify as available choices the manufacturing instruction parameters having the risk rates no greater than the average value, a parameter identifying part that calculates an explanatory variable selection reference value for the manufacturing instruction parameter group and the manufacturing instruction parameters of the available choices with the multiple regression analysis program to identify the manufacturing instruction parameter group or the manufacturing instruction parameters of the available choices having the greater calculated explanatory variable selection reference
    Type: Application
    Filed: February 25, 2009
    Publication date: November 26, 2009
    Inventors: Shinichirou Hanawa, Isao Nakamura, Akiko Tadokoro, Atsunori Hotehama, Yukiko Yamamoto, Haruo Umeki, Akihiro Kondo, Youichi Hamamoto, Kouichi Hiraoka
  • Publication number: 20090237782
    Abstract: In a near-infrared reflective substrate prepared by forming on a transparent substrate a near-infrared reflective film prepared by alternate deposition of low-refractive-index dielectric films and high-refractive-index dielectric films, there is provided a near-infrared reflective substrate characterized in that the transparent substrate is a plate glass or polymer resin sheet, that it is 70% or greater in visible light transmittance defined in JIS R3106-1998, and that it has a maximum value of reflection that exceeds 50% in a wavelength region of 900 nm to 1400 nm.
    Type: Application
    Filed: October 16, 2006
    Publication date: September 24, 2009
    Applicant: Central Glass Company, Limited
    Inventors: Atsushi Takamatsu, Masaaki Yonekura, Hideo Omoto, Isao Nakamura
  • Publication number: 20090157892
    Abstract: A media server device (40) can reproduce each of music compositions held in a built-in storage device (45). Moreover, the media server device (40), while being connected, can stream-distribute a digital content to a network player (51) so as to be reproduced in the network player (51). Reproduced digital content detection means (41) detects a music composition being reproduced. Stream-distribution means (42) stream-distributes data for reproducing the currently reproduced music composition as a notification music composition in the network player (51). Thus, it is possible to provide a media server device, a media server control method, and a program capable of enabling a particular partner to understand the reproduced digital content effectively and in the reproduction format.
    Type: Application
    Filed: September 1, 2006
    Publication date: June 18, 2009
    Applicant: Kabushiki Kaisha Kenwood
    Inventors: Satoru Sekiguchi, Yoshio Sonoda, Isao Nakamura, Masamichi Furukawa, Yoshihisa Mashita, Tomoaki Yoshida, Masahito Watanabe
  • Patent number: 7517583
    Abstract: The present invention relates to a laminated glass having an interlayer film between at least two transparent glass platy bodies. Functional ultra-fine particles of a particle diameter of not greater than 0.2 ?m are dispersed in the interlayer film. The functional ultra-fine particles comprise a single substance of metal, oxide, nitride, sulfide or Sb- or F-doped substance of Sn, Ti, Si, Zn, Zr, Fe, Al, Cr, Co, Ce, In, Ni, Ag, Cu, Pt, Mn, Ta, W, V and Mo, or a composite selected from at least two of these, or a mixture containing an organic resin substance in the single substance or composite, or a coated substance coated with the single substance or composite, or an antimony-doped tin oxide and/or tin-doped indium oxide. An infrared-reflective film that selectively reflects a near-infrared ray and has a sheet resistivity ranging from 1 k?/? to 10 G?/? is formed on at least one surface of the interlayer film or at least one transparent glass platy body.
    Type: Grant
    Filed: September 15, 2004
    Date of Patent: April 14, 2009
    Assignee: Central Glass Company, Limited
    Inventors: Tadashi Onishi, Isao Nakamura, Chiharu Takimoto
  • Patent number: 7467339
    Abstract: A semiconductor integrated circuit (LSI) in which control information for determining a voltage or a width of a pulse produced itself can easily be set in parallel with other LSIs, and set information can be corrected easily. From an external evaluation device, a voltage of an expected value is supplied in overlapping manner to a plurality of LSIs each having a CPU and a flash memory. Each LSI incorporates a comparison circuit comparing an expected voltage value and a boosted voltage generated in itself. The CPU refers to a comparison result and optimizes control data in a data register for changing a boosted voltage. The CPU controls the comparison circuit and the data register and performs trimming in a self-completion manner, thereby making, trimming on a plurality of LSIs easily in a parallel manner and a total test time reduced.
    Type: Grant
    Filed: January 11, 2006
    Date of Patent: December 16, 2008
    Assignees: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Toshihiro Tanaka, Yutaka Shinagawa, Masahiko Kimura, Isao Nakamura
  • Patent number: 7447959
    Abstract: A semiconductor integrated circuit (LSI) in which control information for determining a voltage or a width of a pulse produced itself can easily be set in parallel with other LSIs, and set information can be corrected easily. From an external evaluation device, a voltage of an expected value is supplied in overlapping manner to a plurality of LSIs each having a CPU and a flash memory. Each LSI incorporates a comparison circuit comparing an expected voltage value and a boosted voltage generated in itself. The CPU refers to a comparison result and optimizes control data in a data register for changing a boosted voltage. The CPU controls the comparison circuit and the data register and performs trimming in a self-completion manner, thereby making, trimming on a plurality of LSIs easily in a parallel manner and a total test time reduced.
    Type: Grant
    Filed: April 18, 2007
    Date of Patent: November 4, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Toshihiro Tanaka, Yutaka Shinagawa, Masahiko Kimura, Isao Nakamura
  • Publication number: 20070288817
    Abstract: A semiconductor integrated circuit (LSI) in which control information for determining a voltage or a width of a pulse produced itself can easily be set in parallel with other LSIs, and set information can be corrected easily. From an external evaluation device, a voltage of an expected value is supplied in overlapping manner to a plurality of LSIs each having a CPU and a flash memory. Each LSI incorporates a comparison circuit comparing an expected voltage value and a boosted voltage generated in itself. The CPU refers to a comparison result and optimizes control data in a data register for changing a boosted voltage. The CPU controls the comparison circuit and the data register and performs trimming in a self-completion manner, thereby making, trimming on a plurality of LSIs easily in a parallel manner and a total test time reduced.
    Type: Application
    Filed: April 18, 2007
    Publication date: December 13, 2007
    Inventors: Toshihiro Tanaka, Yutaka Shinagawa, Masahiko Kimura, Isao Nakamura
  • Publication number: 20070026210
    Abstract: The present invention relates to a laminated glass having an interlayer film between at least two transparent glass platy bodies. Functional ultra-fine particles of a particle diameter of not greater than 0.2 ?m are dispersed in the interlayer film. The functional ultra-fine particles comprise a single substance of metal, oxide, nitride, sulfide or Sb— or F-doped substance of Sn, Ti, Si, Zn, Zr, Fe, Al, Cr, Co, Ce, In, Ni, Ag, Cu, Pt, Mn, Ta, W, V and Mo, or a composite selected from at least two of these, or a mixture containing an organic resin substance in the single substance or composite, or a coated substance coated with the single substance or composite, or an antimony-doped tin oxide and/or tin-doped indium oxide. An infrared-reflective film that selectively reflects a near-infrared ray and has a sheet resistivity ranging from 1 k?/? to 10 G?/? is formed on at least one surface of the interlayer film or at least one transparent glass platy body.
    Type: Application
    Filed: September 15, 2004
    Publication date: February 1, 2007
    Applicant: CENTRAL GLASS COMPANY, LIMITED
    Inventors: Tadashi Onishi, Isao Nakamura, Chiharu Takimoto
  • Publication number: 20060119614
    Abstract: The present invention provides a three dimensional graphics processing apparatus 1 for performing an anti-aliasing processing in an sufficient manner, without using the conventional area DDA, by using a line buffer as an area for storing display image data to reduce the required memory area, while the increase of the calculation time is restricted by performing calculation suitable for the polygon edge without degrading the precision of the calculation. In the three dimensional graphics processing apparatus 1, the coordinates of the intersection points between the polygon edge and the scanning lines are calculated from information on the starting vertex and the ending vertex of the polygon edge and information on the scanning lines. The calculation method is changed in accordance with the characteristics of the polygon edge. Further, a blending coefficient for the anti-aliasing process is obtained by calculating an area ratio of an internal region of the polygon occupied within a pixel.
    Type: Application
    Filed: November 15, 2005
    Publication date: June 8, 2006
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Hiroaki Fukui, Isao Nakamura
  • Publication number: 20060123299
    Abstract: A semiconductor integrated circuit (LSI) in which control information for determining a voltage or a width of a pulse produced itself can easily be set in parallel with other LSIs, and set information can be corrected easily. From an external evaluation device, a voltage of an expected value is supplied in overlapping manner to a plurality of LSIs each having a CPU and a flash memory. Each LSI incorporates a comparison circuit comparing an expected voltage value and a boosted voltage generated in itself. The CPU refers to a comparison result and optimizes control data in a data register for changing a boosted voltage. The CPU controls the comparison circuit and the data register and performs trimming in a self-completion manner, thereby making, trimming on a plurality of LSIs easily in a parallel manner and a total test time reduced.
    Type: Application
    Filed: January 11, 2006
    Publication date: June 8, 2006
    Inventors: Toshihiro Tanaka, Yutaka Shinagawa, Masahiko Kimura, Isao Nakamura
  • Patent number: 7049797
    Abstract: In a semiconductor integrated circuit device, having a pair of voltage step-down power supply circuits for active and standby conditions, a first reference voltage is formed by amplifying a fixed voltage formed in a fixed voltage generating circuit with an amplifying circuit which can adjust the voltage gain having a resistance circuit and a switch controlled with a first trimming switch setting signal. An internal step-down voltage, when the internal circuit is in the active condition, is outputted from a first output buffer, which is activated with a first control signal. A second reference voltage is formed by adjusting a combination of threshold voltages of MOSFETs and a switch controlled with a second trimming switch setting signal; and, an internal step-down voltage, when the internal circuit is in the standby condition, is outputted with a second output buffer, which is activated with a second control signal.
    Type: Grant
    Filed: October 2, 2003
    Date of Patent: May 23, 2006
    Assignees: Renesas Technology Corp., Renesas Northern Japan Semiconductor, Inc.
    Inventors: Kenichi Fukui, Mitsuru Hiraki, Takayasu Ito, Isao Nakamura
  • Patent number: 7000160
    Abstract: A semiconductor integrated circuit (LSI) in which control information for determining a voltage or a width of a pulse produced itself can easily be set in parallel with other LSIs, and set information can be corrected easily. From an external evaluation device, a voltage of an expected value is supplied in overlapping manner to a plurality of LSIs each having a CPU and a flash memory. Each LSI incorporates a comparison circuit comparing an expected voltage value and a boosted voltage generated in itself. The CPU refers to a comparison result and optimizes control data in a data register for changing a boosted voltage. The CPU controls the comparison circuit and the data register and performs trimming in a self-completion manner, thereby making, trimming on a plurality of LSIs easily in a parallel manner and a total test time reduced.
    Type: Grant
    Filed: February 27, 2002
    Date of Patent: February 14, 2006
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Toshihiro Tanaka, Yutaka Shinagawa, Masahiko Kimura, Isao Nakamura
  • Publication number: 20050104893
    Abstract: A three dimensional image rendering apparatus for rendering polygons forming a three dimensional object on a two dimensional display screen, comprising: a hidden surface removal section for performing a hidden surface removal process by, when a part or all of the pixels forming the two dimensional display screen belong to a first polygon which is closest to a point of view, updating memory contents in an information memory section to information of the first polygon; and a blending section for obtaining, based on edge identification information for indicating whether the respective pixels are located on an edge of the first polygon and a percentage of an area in the respective pixels occupied by the first polygon as part of information of the first polygon, the color information of the respective pixels from color information as another part of the first polygon.
    Type: Application
    Filed: September 22, 2004
    Publication date: May 19, 2005
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Yasuyuki Kii, Isao Nakamura
  • Publication number: 20040155636
    Abstract: There is provided a semiconductor integrated circuit device which assures high performance and low power consumption through reduction of installation area and realizes automatic voltage adjustment of a couple of voltage step-down power supply circuits for active and standby conditions.
    Type: Application
    Filed: October 2, 2003
    Publication date: August 12, 2004
    Inventors: Kenichi Fukui, Mitsuru Hiraki, Takayasu Ito, Isao Nakamura
  • Patent number: 6753397
    Abstract: The present invention is to provide a resin composition comprising a boron-containing polymer useful as an antifouling coating which does not contain heavy metal from an environmental viewpoint. Thus, the present invention provides a resin composition which comprises a boron-containing polymer having, in a side chain or at a terminal thereof, at least one group represented by the following formula (1): in the formula, R1 is a part of an acid group; R2 groups are the same or different and each represents a substituted or unsubstituted alkyl or aryl; X represents an oxygen or sulfur atom; Y represents a primary to tertiary amine or a heterocyclic compound containing a substituted or unsubstituted nitrogen atom; and n is 1 or 2.
    Type: Grant
    Filed: March 27, 2002
    Date of Patent: June 22, 2004
    Assignee: Nippon Paint Co., Ltd.
    Inventors: Isao Nakamura, Naoki Yamamori