Abstract: An impedance adjustment circuit according to the present invention includes a first input buffer which detects that an input signal exceeds VREFA, a second input buffer which detects that the input signal exceeds VREFB, VREFB being higher than VREFA, a counter circuit A which performs count based on an output from the first input buffer, a counter circuit B which performs count based on an output from the second input buffer, and a termination resistor control circuit which controls impedance of a termination resistor provided in a termination of a transmission path based on the count in the counter circuit A and the count in the counter circuit B.

Abstract: An impedance adjustment circuit according to the present invention includes a first input buffer which detects that an input signal exceeds VREFA, a second input buffer which detects that the input signal exceeds VREFB, VREFB being higher than VREFA, a counter circuit A which performs count based on an output from the first input buffer, a counter circuit B which performs count based on an output from the second input buffer, and a termination resistor control circuit which controls impedance of a termination resistor provided in a termination of a transmission path based on the count in the counter circuit A and the count in the counter circuit B.

Abstract: The present invention provides a semiconductor integrated circuit device, a layout design method and apparatus thereof which enable to select an arbitrary number of grids in primitive cells and minimize the layout area. Each primitive cell is constituted by a core portion having a circuit for realizing a function inherent to the primitive cell and a power supply wiring portion for electrical connection between the core portion and a power supply wiring and electrical connection between cores of different primitive cells. A primitive cell small group is prepared from a plurality of primitive cells having an identical core portion and different numbers of allocatable signal lines in the power supply wiring portion, so that a primitive cell having an appropriate number of signal lines as the power supply wiring portion is selected for layout.