Patents by Inventor Isao Nasuno

Isao Nasuno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6054900
    Abstract: A power amplifier MMIC has a first stage amplifier circuit having a transistor and matching circuits provided on input and output sides of the transistor; a plurality of final stage transistors connected in parallel; a first line connected between adjacent gates of the plurality of final stage amplifiers; a second line, connected between adjacent drains of the plurality of final stage amplifiers, for correcting an input signal phase shift caused by the presence of the first line; and an output matching circuit connected to one of connection points between the second line and the drains, and wherein an output of the first stage amplifier circuit is coupled to one gate of a final stage transistor whose drain is not connected to the output matching circuit, and the first stage amplifier circuit and the plurality of final stage transistors are arranged longitudinally alongside each other.
    Type: Grant
    Filed: March 9, 1999
    Date of Patent: April 25, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kaoru Ishida, Hiroaki Kosugi, Isao Nasuno, Kazuhiko Nakayama
  • Patent number: 5990736
    Abstract: A high frequency power amplifier including: a multi-layer printed-circuit board, a transistor for amplifying an input signal and outputting the amplified signal, a first print circuit pattern for receiving the input signal and supplying the input signal to the transistor, a second print circuit pattern for supplying a supply voltage to the transistor, a ground terminal, and concentrated constant elements connected to the transistor on the multi-layer printed-circuit board is disclosed, wherein at least two layers of the multi-layer printed-circuit board are connected to the ground terminal, the first and second print circuit patterns are sandwiched on one layer of the multi-layer print circuit between the at least two layers, a first shielding circuit pattern, connected to the ground terminal, arranged around the first print circuit pattern on the one layer is further provided; and a second shielding circuit pattern, connected to the ground terminal, arranged around the second print circuit pattern on the one
    Type: Grant
    Filed: May 6, 1998
    Date of Patent: November 23, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Isao Nasuno, Yohei Ichikawa