Abstract: A complementary metal-oxide semiconductor integrated circuit device comprises a plurality of pairs of N- and P-channel metal-oxide semiconductor transistors (01a, 02a, 03a, 04a; 01b, 02b, 03b, 04b). The plurality of pairs are juxtaposed with respect to each other and no isolation areas are formed between the respective pairs. A single pair or a series of pairs out of the plurality of pairs constitute a functional device (30). The gate electrodes (311a, 311b) of the N- and P-channel metal-oxide semiconductor transistors in the pair adjacent to the functional device (30) are held in relatively negative (GND) and positive (V.sub.DD) potential voltages, respectively, so that the functional device (30) is electrically isolated from the remaining portions.

Abstract: A semiconductor integrated circuit device with a complementary type internal logic function element used as a master slice type gate array LSI is disclosed having two transmission gates. A plurality of pairs of transistors are utilized with each pair comprising a first conductivity type transistor and a second conductivity type transistor. A first transmission gate is constructed with the first conductivity type transistor of one pair of transistors out of two pairs of these transistor pairs and the second conductivity type transistor of the other pair. Second transmission gate is constructed with the first conductivity type transistor of the other transistor pair and the second conductivity type transistor of the first transistor pair so that an area required for constructing the two transmission gates is reduced in order to increase the degree of integration.

Abstract: A complementary metal-oxide semiconductor master slice integrated circuit comprises a plurality of basic cells (41, 141; 42, 142; . . . ) in an internal functional gate region (22), each basic cell, which is a basic repetition unit, including a single P-channel metal-oxide semiconductor (41, 42, . . . ) and a single N-channel metal-oxide semiconductor (141, 142, . . . ) which are disposed linearly with respect to each other through an electrical isolation region. The plurality of basic cells are equidistantly disposed in parallel in a traverse direction of the internal functional gate region (22), without disposing any electrical isolation regions between the basic cells, so that the positions (101.about.108, 91.about.98) where longitudinal wirings are to be placed in a wiring zone (31, 32) correspond to the basic cells in a one-to-one manner.