Abstract: A computer system includes a CPU, a memory circuit storing at least instruction codes, an error checking circuit checking an error of an instruction code read from the memory circuit according to an instruction address supplied from the CPU, a code storing circuit storing data to be outputted to the CPU instead of data from the memory when an error occurs, a selection circuit in which inputs are coupled to the memory circuit and the code storing circuit, and selectively outputting data from the code storing circuit when an error is detected by the error checking circuit, a bus connecting the selection circuit to the CPU, and an instruction error register storing a value indicating that an error occurs when the error is detected by the error checking circuit.

Abstract: An error processing method processes an error generated on a bus of a CPU, by inputting a bus error that is generated on at least one of an instruction bus and a data bus of the CPU to the CPU by a bus error input part, counting the bus error by a bus error counter part of the CPU, and specifying a region of a memory part that is coupled to the CPU based on a value of the bus error counter part.

Abstract: A computer system includes a CPU, a memory circuit storing at least instruction codes, an error checking circuit checking an error of an instruction code read from the memory circuit according to an instruction address supplied from the CPU, a code storing circuit storing data to be outputted to the CPU instead of data from the memory when an error occurs, a selection circuit in which inputs are coupled to the memory circuit and the code storing circuit, and selectively outputting data from the code storing circuit when an error is detected by the error checking circuit, a bus connecting the selection circuit to the CPU, and an instruction error register storing a value indicating that an error occurs when the error is detected by the error checking circuit.

Abstract: An error processing method processes an error generated on a bus of a CPU, by inputting a bus error that is generated on at least one of an instruction bus and a data bus of the CPU to the CPU by a bus error input part, counting the bus error by a bus error counter part of the CPU, and specifying a region of a memory part that is coupled to the CPU based on a value of the bus error counter part.

Abstract: A threshold value serving as a reference for judging a decrease in power source voltage supplied to a semiconductor device is registered as digital data, detection data corresponding to a magnitude of the power source voltage is outputted by executing an analog/digital conversion of the power source voltage, the threshold value is compared with the detection data, and there is outputted a control signal controlling as to whether or not setting of the semiconductor device should be set in an initial state in accordance with the compared result.

Abstract: A semiconductor integrated circuit device capable of lengthening a life of a FeRAM. A RAM stores the same data as those of the FeRAM in the same address as that of the FeRAM. An FF (flip-flop) section stores validity of the data at each address on the RAM. When data at a specified address are valid with reference to the FF section at the time of data reading, a data access controller allows data reading from the RAM in place of the FeRAM.

Abstract: A floating type magnetic head comprises a slider made of a nonmagnetic material and a magnetic core inserted in a core inserting groove formed through the slider so that the magnetic core is bonded at the inserted position by a bonding agent consisting of glass. A slider groove is formed at a central part of the slider, while floating surfaces are formed on both sides of the slider groove, with the core inserting groove formed in communication with the slider groove.