Abstract: An n-bit analog-to-digital converter includes a comparator that compares an analog input voltage with a comparison voltage; and a digital-to-analog converter that generates the comparison voltage in response to a result of the comparator, wherein the analog-to-digital converter outputs n-bit digital data corresponding to the analog input voltage, and wherein the analog-to-digital converter outputs a self-diagnosis result in such a way that the digital-to-analog converter generates a self-diagnosis voltage in response to the n-bit digital data and the comparator compares the analog input voltage with the self-diagnosis voltage.

Abstract: An n-bit analog-to-digital converter includes a comparator that compares an analog input voltage with a comparison voltage; and a digital-to-analog converter that generates the comparison voltage in response to a result of the comparator, wherein the analog-to-digital converter outputs n-bit digital data corresponding to the analog input voltage, and wherein the analog-to-digital converter outputs a self-diagnosis result in such a way that the digital-to-analog converter generates a self-diagnosis voltage in response to the n-bit digital data and the comparator compares the analog input voltage with the self-diagnosis voltage.

Abstract: An analog-to-digital converter includes an input terminal to which an analog input voltage is input, a digital-to-analog converter unit, a comparator that compares the analog input voltage and an output voltage of the digital-to-analog converter unit with each other, a successive approximation register that stores a conversion result output from the comparator, a generator unit that generates added digital data and subtracted digital data, the added digital data and the subtracted digital data being obtained by adding and subtracting the conversion result to and from the conversion result retained by the successive approximation register, respectively, and a determination unit that determines whether or not a failure is occurring, by using a result of the comparison between the analog input voltage and output levels obtained by the digital-to-analog converter unit converting the added digital data and the subtracted digital data.

Abstract: An analog-to-digital converter includes an input terminal to which an analog input voltage is input, a digital-to-analog converter unit, a comparator that compares the analog input voltage and an output voltage of the digital-to-analog converter unit with each other, a successive approximation register that stores a conversion result output from the comparator, a generator unit that generates added digital data and subtracted digital data, the added digital data and the subtracted digital data being obtained by adding and subtracting the conversion result to and from the conversion result retained by the successive approximation register, respectively, and a determination unit that determines whether or not a failure is occurring, by using a result of the comparison between the analog input voltage and output levels obtained by the digital-to-analog converter unit converting the added digital data and the subtracted digital data.

Abstract: One exemplary embodiment includes a difference image generation device including a measurement unit and a scaling unit. The measurement unit measures a variation width of pixel values of a difference image signal obtained by performing subtraction processing on first and second input image signals. The scaling unit scales each pixel value of the difference image signal based on a measurement result of the variation width so that the difference image signal can be represented in grayscale using a predetermined bit width, and outputs a difference image signal subjected to scaling.

Abstract: A motion vector display circuit includes a motion vector detection circuit that detects a motion vector between frame images, and a norm calculation circuit that calculates the length of a motion vector detected by the motion vector detection circuit. The length of the detected motion vector is converted into a luminance component of a display signal, a first component of the motion vector is converted into a first chrominance component of the display signal, a second component of the motion vector is converted into a second chrominance component of the display signal, and the motion vector is displayed using the display signal.

Abstract: An image processing device includes a pixel value read out unit which reads out a pixel value of a target pixel, a pixel value change unit which changes a pixel value of a noticeable pixel, the noticeable pixel being at least one pixel of adjacent pixels adjacent to the target pixel, and a coordinate specify unit which specifies a position of the target pixel in an image, the target pixel having the noticeable pixel as the adjacent pixel. The pixel value of the noticeable pixel is changed.

Abstract: One exemplary embodiment includes a difference image generation device including a measurement unit and a scaling unit. The measurement unit measures a variation width of pixel values of a difference image signal obtained by performing subtraction processing on first and second input image signals. The scaling unit scales each pixel value of the difference image signal based on a measurement result of the variation width so that the difference image signal can be represented in grayscale using a predetermined bit width, and outputs a difference image signal subjected to scaling.

Abstract: A picture frame generating circuit has: a coordinate value calculation processor that calculates frame start position (X, Y), picture end position (X, Y), frame end position (X, Y) using calculation start signal as activation signal, based on picture position (X, Y) registers, picture size (X, Y) registers and frame size register which are written through a data bus, the processor allowing frame color data to be written into frame color register to designate the color of frame through the data bus: and a selection circuit of frame and picture to which the frame start position (X, Y), picture end position (X, Y), frame end position (X, Y), picture position (X, Y) registers, frame color data, picture data, horizontal display position and vertical display position are input, the circuit selecting the picture data or frame color data and outputs the selected one as display data.

Abstract: A video transmission apparatus in which an n (the n represents an integer of 2 or more) number of different video data (13), (15), (17), (19) are transmitted via a single transmission line (8) from a plurality of video signal output sections (14), (16), (18), (20) to a video display device (5) and on the video display device (5), the video data that is indicated by a video data switching device (1) is selectively displayed, wherein the video display device (5) comprising; a latch signal generation circuit (40) for generating a latch signal (27) for latching either one of the n number of different video data (13), (15), (17), (19) on the transmission line (8) in accordance with a video switching signal output (2) from the video data switching device (1), and a latch circuit (37) for latching a prescribed video data on the transmission line (8) by the latch signal (27).

Abstract: To provide a data processor having a bus means whereby high-speed data exchange can be performed stably among a plurality of inner circuits (1 to 5) without dissipation of useless current, the bus means comprises more than one bus selectors (7 and 8) cascade-connected into a loop by way of bus lines. Each (7) of the bus selectors outputs bus data supplied from a preceding bus selector (8) as bus data to be supplied towards a following bus selector (8) when none of the inner circuits (1 to 3) connected to the bus selector (7) enables an output enable signal, and outputs output data of one of the inner circuits (1 to 3) connected to the bus selector (7) as the bus data to be supplied towards the following bus selector (8) when the inner circuit enables the output enable signal.

Abstract: A semiconductor integrated circuit includes a register for storing a designated value and a delay element group for delaying an input signal by a delay quantity set based on the designated value to output the signal delayed by the delay quantity as a delay signal. The semiconductor integrated circuit further includes a PLL circuit for inputting the delay signal and a clock signal and for outputting a phase adjustment signal. In this case, the phase adjustment signal is supplied to the delay element group as the input signal.