Abstract: A logic circuit comprises a first terminal for receiving an input data signal, a second terminal for receiving a clock signal, a first latch circuit coupled to the first and second terminals for latching the input data signal responsive to the clock signal, a second latch circuit coupled to the first latch circuit for latching an output signal of the first latch circuit, a third terminal for outputting an output data signal which is output from the second latch circuit, and a selecting part coupled to the third terminal for selectively feeding back the output data signal to the first latch circuit in a first mode and for cutting off the feedback of the output data signal to the first latch circuit in a second mode, where the logic circuit operates as a toggle flip-flop in the first mode and operates as a delay flip-flop in the second mode. The input data signal received by the first terminal selectively identifies one of the two modes of the flip-flop.

Abstract: A master-slave flip-flop circuit is made up of a master part which holds a data signal responsive to a clock signal and outputs the held data signal in the form of complementary output signals, and a slave part which holds the complementary output signals responsive to the clock signal and outputs at least one of the held complementary output signals. The complementary output signals of the master part have a logic amplitude which is smaller than a logic amplitude of the output signal of the slave part to ensure correct operation even when the data signal and the clock signal have high frequencies.

Abstract: A gate array device forms an arbitray logic circuit depending on interconnections formed thereon, and comprises a semiconductor chip having an approximate rectangular shape, an input terminal region including a plurality of input terminals formed at a peripheral portion of the semiconductor chip, an output terminal region including a plurality of output terminals formed at a peripheral portion of the semiconductor chip, and a macro cell region including a plurality of macro cells formed at a central portion of the semiconductor chip. The macro cells include first macro cells and second macro cells, where each of the first macro cells include a minimum number of elements for forming a master part of a master-slave flip-flop circuit and each of the second macro cells include at least a minimum number of elements for forming a slave part of the master-slave flip-flop circuit. The first macro cells and the second macro cells make macro cell pairs and are regularly arranged within the macro cell region.

Abstract: An ECL transistor pair is connected in parallel with a third transistor. A complementary signal is applied to the transistor pair. A high level of a signal that is applied to the third transistor is effectively higher than a high level of the input to the pair of transistors; and a low level of the signal applied to the third transistor is effectively lower than the high level of the input to the pair of transistors. The low level input to the third transistor enables the ECL circuit to output the complementary input signal and assures high speed ECL operation. The high level of the input to the third transistor disables the ECL circuit from outputting the complementary input signal.