Abstract: The terminals that oppose each other when substrates are bonded are designed to be reliably joined. Comprised in a semiconductor device design system are a numerical value acquiring part, which acquires the respective numerical values of a plurality of calculation parameters, a junction estimating part, which, in the case in which a plurality of substrates has been pressed at a prescribed pressure so that the bump front end faces come into contact, estimates whether or not the respective mutually opposing bumps will be joined based on the respective numerical values of the calculation parameters acquired by the numerical value acquiring part, and a change processing part, which, in the case in which it has been estimated by the junction estimating part that any of the bumps will not be joined, gives a warning or performs processing so as to change the numerical value of at least one calculation parameter among the plurality of calculation parameters.

Abstract: The terminals that oppose each other when substrates are bonded are designed to be reliably joined. Comprised in a semiconductor device design system are a numerical value acquiring part, which acquires the respective numerical values of a plurality of calculation parameters, a junction estimating part, which, in the case in which a plurality of substrates has been pressed at a prescribed pressure so that the bump front end faces come into contact, estimates whether or not the respective mutually opposing bumps will be joined based on the respective numerical values of the calculation parameters acquired by the numerical value acquiring part, and a change processing part, which, in the case in which it has been estimated by the junction estimating part that any of the bumps will not be joined, gives a warning or performs processing so as to change the numerical value of at least one calculation parameter among the plurality of calculation parameters.

Abstract: The terminals that oppose each other when substrates are bonded are designed to be reliably joined. Comprised in a semiconductor device design system are a numerical value acquiring part, which acquires the respective numerical values of a plurality of calculation parameters, a junction estimating part, which, in the case in which a plurality of substrates has been pressed at a prescribed pressure so that the bump front end faces come into contact, estimates whether or not the respective mutually opposing bumps will be joined based on the respective numerical values of the calculation parameters acquired by the numerical value acquiring part, and a change processing part, which, in the case in which it has been estimated by the junction estimating part that any of the bumps will not be joined, gives a warning or performs processing so as to change the numerical value of at least one calculation parameter among the plurality of calculation parameters.

Abstract: Substrates are aligned and then bonded to each other. A substrate bonding apparatus includes a deformer that deforms at least a first one of two substrates that are to be bonded to each other in order to correct misalignment between the two substrates, a holder that holds the deformed first substrate in the deformed state achieved by the deformer, a transporter that transports the holder from a position at which the deformed first substrate is held by the holder while the first substrate remains deformed, and a bonder that bonds the first substrate that has been transported by the transporter to the second substrate.

Abstract: Provided is a multi-layered semiconductor apparatus with improved heat diffusion and improved heat release. The multi-layered semiconductor apparatus (100) includes a plurality of layered semiconductor chips (20-1, 20-2) that each include at least one circuit region, and the circuit regions are arranged such that heat generated by the circuit regions as a result of the circuit regions being driven is spread out. The multi-layered semiconductor apparatus (100) further comprises a heat releasing section (50) that releases the heat generated by the circuit regions, and the circuit regions are arranged such that there is less thermal resistance between the heat releasing section and circuit regions that generate a greater amount of heat per unit area.

Abstract: Provided is a multi-layered semiconductor apparatus with improved heat diffusion and improved heat release. The multi-layered semiconductor apparatus (100) includes a plurality of layered semiconductor chips (20-1, 20-2) that each include at least one circuit region, and the circuit regions are arranged such that heat generated by the circuit regions as a result of the circuit regions being driven is spread out. The multi-layered semiconductor apparatus (100) further comprises a heat releasing section (50) that releases the heat generated by the circuit regions, and the circuit regions are arranged such that there is less thermal resistance between the heat releasing section and circuit regions that generate a greater amount of heat per unit area.

Abstract: At least a part of a heat radiation member (9) connected to a DRAM (11) for radiating heat of the DRAM (11) is exposed from a protection member (4) arranged to surround the DRAM and the heat radiation member (9) so as to protect the DRAM (11). Thus, it is possible to provide a semiconductor device having a preferable heat radiation performance.

Abstract: The terminals that oppose each other when substrates are bonded are designed to be reliably joined. Comprised in a semiconductor device design system are a numerical value acquiring part, which acquires the respective numerical values of a plurality of calculation parameters, a junction estimating part, which, in the case in which a plurality of substrates has been pressed at a prescribed pressure so that the bump front end faces come into contact, estimates whether or not the respective mutually opposing bumps will be joined based on the respective numerical values of the calculation parameters acquired by the numerical value acquiring part, and a change processing part, which, in the case in which it has been estimated by the junction estimating part that any of the bumps will not be joined, gives a warning or performs processing so as to change the numerical value of at least one calculation parameter among the plurality of calculation parameters.

Abstract: Provided is a multi-layered semiconductor apparatus with improved heat diffusion and improved heat release. The multi-layered semiconductor apparatus (100) includes a plurality of layered semiconductor chips (20-1, 20-2) that each include at least one circuit region, and the circuit regions are arranged such that heat generated by the circuit regions as a result of the circuit regions being driven is spread out. The multi-layered semiconductor apparatus (100) further comprises a heat releasing section (50) that releases the heat generated by the circuit regions, and the circuit regions are arranged such that there is less thermal resistance between the heat releasing section and circuit regions that generate a greater amount of heat per unit area.

Abstract: Provided is a multi-layered semiconductor apparatus with improved heat diffusion and improved heat release. The multi-layered semiconductor apparatus (100) includes a plurality of layered semiconductor chips (20-1, 20-2) that each include at least one circuit region, and the circuit regions are arranged such that heat generated by the circuit regions as a result of the circuit regions being driven is spread out. The multi-layered semiconductor apparatus (100) further comprises a heat releasing section (50) that releases the heat generated by the circuit regions, and the circuit regions are arranged such that there is less thermal resistance between the heat releasing section and circuit regions that generate a greater amount of heat per unit area.

Abstract: Provided is a substrate holder pair comprising a first substrate holder that has a first holding portion holding a first substrate; a second substrate holder that has a second holding portion holding a second substrate to be bonded with the first substrate and that, together with the first substrate holder, sandwiches the first substrate and the second substrate; an engaging member that causes the first substrate holder to engage with the second substrate holder; and a dust inhibiting section inhibits dust generated by the engaging of the engaging member from entering between the first holding portion and the second holding portion.

Abstract: Provided is a substrate holder system comprising a first substrate holder that holds a first substrate; an engaging member provided on the first substrate holder; a second substrate holder that holds a second substrate and can, together with the first substrate holder, sandwich the first substrate and the second substrate; an engagement receiving member that is provided on the second substrate holder and engages with the engaging member; and a dust restricting means for restricting generation of dust caused by the engagement of the engaging member and the engagement receiving member.

Abstract: Between a logic LSI (4) arranged on one side of a DRAM (1) and jointed to the DRAM and a radiating member (6) arranged on the other side of the DRAM (1) for irradiating the heats of the DRAM (1) and the logic LSI (4), there is disposed a heat bypass passage (5), which extends inbetween while bypassing the DRAM (1). Thus, it is possible to provide a semiconductor device, which can irradiate the heat generated from the logic LSI such as CPU or GPU thereby to reduce the temperature rise and the temperature distribution.

Abstract: Between a logic LSI (4) arranged on one side of a DRAM (1) and jointed to the DRAM and a radiating member (6) arranged on the other side of the DRAM (1) for irradiating the heats of the DRAM (1) and the logic LSI (4), there is disposed a heat bypass passage (5), which extends inbetween while bypassing the DRAM (1). Thus, it is possible to provide a semiconductor device, which can irradiate the heat generated from the logic LSI such as CPU or GPU thereby to reduce the temperature rise and the temperature distribution.

Abstract: Management of the holding member that holds the semiconductor substrate is efficiently implemented. Provided is a holding member management apparatus that manages a substrate holding member that holds a semiconductor substrate in a manufacturing apparatus that manufactures a stacked semiconductor apparatus by joining a plurality of semiconductor substrates; comprising a history storing part that stores the usage history of the substrate holding member in association with identification information that specifies the substrate holding member and a holding member specifying part that specifies and outputs identification information of the substrate holding member whose usage is to be suspended based on the usage history stored in the history storing part.

Abstract: The terminals that oppose each other when substrates are bonded are designed to be reliably joined. Comprised in a semiconductor device design system are a numerical value acquiring part, which acquires the respective numerical values of a plurality of calculation parameters, a junction estimating part, which, in the case in which a plurality of substrates has been pressed at a prescribed pressure so that the bump front end faces come into contact, estimates whether or not the respective mutually opposing bumps will be joined based on the respective numerical values of the calculation parameters acquired by the numerical value acquiring part, and a change processing part, which, in the case in which it has been estimated by the junction estimating part that any of the bumps will not be joined, gives a warning or performs processing so as to change the numerical value of at least one calculation parameter among the plurality of calculation parameters.

Abstract: Provided is a multi-layered semiconductor apparatus with improved heat diffusion and improved heat release. The multi-layered semiconductor apparatus (100) includes a plurality of layered semiconductor chips (20-1, 20-2) that each include at least one circuit region, and the circuit regions are arranged such that heat generated by the circuit regions as a result of the circuit regions being driven is spread out. The multi-layered semiconductor apparatus (100) further comprises a heat releasing section (50) that releases the heat generated by the circuit regions, and the circuit regions are arranged such that there is less thermal resistance between the heat releasing section and circuit regions that generate a greater amount of heat per unit area.

Abstract: At least a part of a heat radiation member (9) connected to a DRAM (11) for radiating heat of the DRAM (11) is exposed from a protection member (4) arranged to surround the DRAM and the heat radiation member (9) so as to protect the DRAM (11). Thus, it is possible to provide a semiconductor device having a preferable heat radiation performance.

Abstract: Between a logic LSI (4) arranged on one side of a DRAM (1) and jointed to the DRAM and a radiating member (6) arranged on the other side of the DRAM (1) for irradiating the heats of the DRAM (1) and the logic LSI (4), there is disposed a heat bypass passage (5), which extends inbetween while bypassing the DRAM (1). Thus, it is possible to provide a semiconductor device, which can irradiate the heat generated from the logic LSI such as CPU or GPU thereby to reduce the temperature rise and the temperature distribution.

Abstract: The polishing body is attached to a substrates. The polishing body has a structure in which a polishing pad, a hard elastic member and a soft members are laminated in that order from the side of the polishing surface. For example, an IC1000 (commercial name) manufactured by Rodel, Inc. is used as the polishing pad. For example, a stainless steel plate is used as the hard elastic member. A Suba400 (commercial name) manufactured by Rodel, Inc. is used as the soft members. The polishing pad 6 has grooves in the polishing surface side. The residual thickness d of the areas of the grooves in the polishing pad is set so as to satisfy the condition 0 mm<d?0.6 mm. As a result, the ability to eliminate steps can be increased, thus allowing the “local pattern flatness” to be improved, while ensuring the “global removal uniformity”; furthermore, a polishing body with a long useful life can be obtained.