Patents by Inventor Isao Takayanagi

Isao Takayanagi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12294793
    Abstract: A solid-state imaging device, a method for driving a solid-state imaging device and an electronic apparatus are capable of reducing kTC noise of a LCG signal, preventing a drop in SNR at the conjunction point between a HCG signal and the LCG signal, and eventually achieving improved image quality. At a start of a reset period, first and second reset transistors are switched into a conduction state. During a predetermined first period after the reset period starts, the first reset line is kept connected to a reset potential. After the first period elapses, the second reset transistor is switched into a non-conduction state to switch the first reset line into a floating state, so that the first reset line has high impedance. After a second period elapses and when the reset period ends, the first reset transistor is switched into the non-conduction state.
    Type: Grant
    Filed: April 28, 2023
    Date of Patent: May 6, 2025
    Assignees: BRILLNICS SINGAPORE PTE. LTD., THE RITSUMEIKAN TRUST
    Inventors: Kazuki Tatsuta, Shunsuke Okura, Ken Miyauchi, Hideki Owada, Sangman Han, Isao Takayanagi
  • Publication number: 20240397233
    Abstract: A pixel is formed by a photoelectric conversion film that converts light into a photogenerated current and a semiconductor pixel circuit. The photoelectric conversion film and the semiconductor pixel circuit are stacked and electrically coupled within the pixel. The photoelectric conversion film has an infrared NIR sensitivity. The semiconductor pixel circuit includes a pixel analog circuit that detects the photoelectric conversion current, a sample-and-hold circuit, an ADC, in-pixel logic, digital memory and the like.
    Type: Application
    Filed: May 23, 2024
    Publication date: November 28, 2024
    Inventors: Isao TAKAYANAGI, Rimon IKENO, Toshihiko ISOZAKI, Masato NAGAMATSU, Kazuya MORI, Hirofumi ABE, Masayuki UNO
  • Publication number: 20240365027
    Abstract: In a pixel signal processing part, a first input switch and an output switch are turned on and off in phase. When the first input switch and the output switch are ON and the second input switch is OFF, a first auto-zero switch and a second auto-zero switch are kept in the ON state to connect the second node to the reference potential (GND), so that a sampling capacitor, a feedback capacitor, and an auto-zero capacitor are operated in respective operation ranges of the capacitors, and the feedback capacitor is kept constant according to a difference of the input pixel signals, thereby making the output of the amplifier in linear response to the input signal.
    Type: Application
    Filed: April 25, 2024
    Publication date: October 31, 2024
    Inventors: Ryotaro HOTTA, Shunsuke OKURA, Ken MIYAUCHI, Hideki OWADA, Sangman HAN, Isao TAKAYANAGI
  • Patent number: 12107095
    Abstract: One object of the present invention is to provide a solid-state imaging device, a method for fabricating a solid-state imaging device, and an electronic apparatus that implement both a wide dynamic range and a high sensitivity. A storage capacitor serving as a storage capacitance element includes a first electrode and a second electrode on a second substrate surface side. The first electrode is formed of a p+ region (the second conductivity type semiconductor region) formed in the surface of a second substrate surface of a substrate, and the second electrode is formed above the second substrate surface so as to be opposed at a distance to the first electrode in the direction perpendicular to the substrate surface. The first electrode and the second electrode are arranged so as to spatially overlap with a photoelectric conversion part in the direction perpendicular to the substrate surface.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: October 1, 2024
    Assignees: BRILLNICS SINGAPORE PTE. LTD., TOHOKU TECHNO ARCH CO., LTD.
    Inventors: Shunsuke Okura, Isao Takayanagi, Kazuya Mori, Ken Miyauchi, Shigetoshi Sugawa
  • Publication number: 20240196116
    Abstract: A pixel circuit 200 includes a readable pixel 210, a comparator 220, and a selector counter circuit 230. The readable pixel 210 performs photoelectric conversion at a photodiode PD11 and produces a readable signal corresponding to an illuminance condition of incident light. The readable pixel 210 includes an overflow path extending to a floating diffusion FD11. The comparator 220 compares a voltage signal (SFout) read out from the readable pixel 210 against a reference signal Vref and outputs a comparison result signal Vout indicating the result of the comparison. The selector counter circuit 230 includes a selector circuit for selecting an external clock or the output Vout from the comparator and a counter circuit for counting the output from the selector circuit.
    Type: Application
    Filed: April 4, 2022
    Publication date: June 13, 2024
    Inventors: Ken MIYAUCHI, Isao TAKAYANAGI, Kazuya MORI
  • Publication number: 20240089635
    Abstract: Provided are a solid-state imaging device, a method for driving a solid-state imaging device and an electronic apparatus that are capable of achieving reduced noise at a voltage sample-and-hold node without requiring an increase in capacitance of a signal holding capacitor for sampling and holding voltage. A solid-state imaging device includes: a photoelectric conversion reading part; an amplifier circuit; a signal holding part including a sample-and-hold signal holding capacitor for holding the read-out voltage signal amplified by the amplifier circuit and outputting the held voltage signal; a first in-pixel signal line to which a low-gain read-out voltage signal is output; and a second in-pixel signal line connected to the output side of the amplifier circuit and to which a high-gain read-out voltage signal is output. A second differential transistor of a differential transistor pair of the amplifier circuit also serves as a source follower transistor.
    Type: Application
    Filed: September 13, 2023
    Publication date: March 14, 2024
    Inventor: Isao TAKAYANAGI
  • Publication number: 20240089631
    Abstract: A solid-state imaging device includes: an output buffer part adapted to convert charge at an output node into a voltage signal corresponding to the amount of the charge, and output an active comparison result signal when the voltage signal and a first reference signal are the same level; an output buffer part adapted to convert the charge at the output node into a voltage signal corresponding to the amount of the charge, compare the voltage signal with the first reference signal, and output the active comparison result signal when the voltage signal and the first reference signal are the same level; the holding signal readout part disposed between the input node of the signal holding part and the feeding line of the second reference signal, conduction or non-conduction of the holding signal readout part being controlled depending on the comparison result signal outputted by the output buffer part.
    Type: Application
    Filed: September 13, 2023
    Publication date: March 14, 2024
    Inventor: Isao TAKAYANAGI
  • Publication number: 20240022836
    Abstract: Provided are a solid-state imaging device, a method for driving a solid-state imaging device, and an electronic apparatus that are capable of selecting a pixel operating mode between a RS mode and a GS mode and switching a conversion gain read-out mode, where signals produced with different conversion gains are read, among several options depending on a scene. As a result, the solid-state imaging device, the method for driving the solid-state imaging device and the electronic apparatus can minimize a drop in SNR at the conjunction point between a HCG signal and a LCG signal and also achieve high full well capacity and little dark noise. In a solid-state imaging device, a pixel part includes pixels arranged in a matrix pattern, and each pixel includes a photoelectric conversion reading part. The solid-state imaging device is capable of performing rolling shutter (RS) and global shutter (GS).
    Type: Application
    Filed: July 12, 2023
    Publication date: January 18, 2024
    Inventors: Ken MIYAUCHI, Hideki OWADA, Kazuya MORI, Isao TAKAYANAGI
  • Patent number: 11849235
    Abstract: Provided are a solid-state imaging device, a method for driving a solid-state imaging device, and an electronic apparatus capable of reading signals produced with different conversion gains and having different signal directions. A pixel signal processing part 400 includes a first reading part 410 and a second reading part 420. Of a pixel signal PIXOUT input into an input node ND401, the first reading part 410 inverts the signal direction of a first-conversion-gain signal (HCGRST, HCGSIG) and outputs an inverted first-conversion-gain signal (HCGRST, HCGSIG), which has been subjected to inversion and amplification, to an AD converting part 430 via a connection node ND402. Of the pixel signal PIXOUT input into the input node ND401, the second reading part 420 keeps the signal direction of a second-conversion-gain signal (LCGSIG, LCGRST) unchanged, and outputs a non-inverted second-conversion-gain signal (LCGSIG, LCGRST) to the AD converting part 430 via the connection node ND402.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: December 19, 2023
    Assignees: Brillnics Singapore Pte. Ltd., THE RITSUMEIKAN TRUST
    Inventors: Shunsuke Okura, Ai Otani, Ken Miyauchi, Hideki Owada, Sangman Han, Isao Takayanagi
  • Publication number: 20230353898
    Abstract: A solid-state imaging device, a method for driving a solid-state imaging device and an electronic apparatus are capable of reducing kTC noise of a LCG signal, preventing a drop in SNR at the conjunction point between a HCG signal and the LCG signal, and eventually achieving improved image quality. At a start of a reset period, first and second reset transistors are switched into a conduction state. During a predetermined first period after the reset period starts, the first reset line is kept connected to a reset potential. After the first period elapses, the second reset transistor is switched into a non-conduction state to switch the first reset line into a floating state, so that the first reset line has high impedance. After a second period elapses and when the reset period ends, the first reset transistor is switched into the non-conduction state.
    Type: Application
    Filed: April 28, 2023
    Publication date: November 2, 2023
    Inventors: Kazuki TATSUTA, Shunsuke OKURA, Ken MIYAUCHI, Hideki OWADA, Sangman HAN, Isao TAKAYANAGI
  • Patent number: 11671730
    Abstract: In a pixel 200, a floating diffusion FD11 and a first capacitor CS11 are selectively connected to each other via a first connection element LG11-Tr, to change the capacitance of the floating diffusion FD11 between a first capacitance and a second capacitance, thereby changing the conversion gain between a first conversion gain (HCG) corresponding to the first capacitance and a second conversion gain (MCG) corresponding to the second capacitance. The floating diffusion FD11 and a second capacitor CS12 are connected together through a second connection element SG11-Tr to change the capacitance of the floating diffusion FD11 to a third capacitance, thereby changing the conversion gain of the source following transistor SF11-Tr to a third conversion gain (LCG) corresponding to the third capacitance.
    Type: Grant
    Filed: May 20, 2022
    Date of Patent: June 6, 2023
    Assignee: BRILLNICS SINGAPORE PTE. LTD.
    Inventors: Ken Miyauchi, Isao Takayanagi
  • Publication number: 20220408047
    Abstract: Provided are a solid-state imaging device, a method for driving a solid-state imaging device, and an electronic apparatus capable of reading signals produced with different conversion gains and having different signal directions. A pixel signal processing part 400 includes a first reading part 410 and a second reading part 420. Of a pixel signal PIXOUT input into an input node ND401, the first reading part 410 inverts the signal direction of a first-conversion-gain signal (HCGRST, HCGSIG) and outputs an inverted first-conversion-gain signal (HCGRST, HCGSIG), which has been subjected to inversion and amplification, to an AD converting part 430 via a connection node ND402. Of the pixel signal PIXOUT input into the input node ND401, the second reading part 420 keeps the signal direction of a second-conversion-gain signal (LCGSIG, LCGRST) unchanged, and outputs a non-inverted second-conversion-gain signal (LCGSIG, LCGRST) to the AD converting part 430 via the connection node ND402.
    Type: Application
    Filed: June 16, 2022
    Publication date: December 22, 2022
    Inventors: Shunsuke OKURA, Ai OTANI, Ken MIYAUCHI, Hideki OWADA, Sangman HAN, Isao TAKAYANAGI
  • Publication number: 20220385852
    Abstract: In a pixel 200, a floating diffusion FD11 and a first capacitor CS11 are selectively connected to each other via a first connection element LG11-Tr, to change the capacitance of the floating diffusion FD11 between a first capacitance and a second capacitance, thereby changing the conversion gain between a first conversion gain (HCG) corresponding to the first capacitance and a second conversion gain (MCG) corresponding to the second capacitance.
    Type: Application
    Filed: May 20, 2022
    Publication date: December 1, 2022
    Inventors: Ken MIYAUCHI, Isao TAKAYANAGI
  • Patent number: 11350044
    Abstract: A pixel PXL includes a first photodiode PDSL and a second photodiode PSLS having different well capacities and responsivities, transfer transistors TGSL-Tr, TGLS-Tr for transferring the charges stored in the photodiodes to a floating diffusion FD, and a capacitance changing part 80 for changing the capacitance of the floating diffusion depending on a capacitance changing signal. The first well capacity of the first photodiode PDSL is smaller than the second well capacity of the second photodiode PDLS, and the first responsivity of the first photodiode PDSL is larger than the second responsivity of the second photodiode PDLS. With these configurations, it becomes possible to realize a widened dynamic range, prevent the read-out noise from affecting the performance, and eventually achieve improved image quality.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: May 31, 2022
    Assignee: BRILLNICS SINGAPORE PTE. LTD.
    Inventors: Kazuya Mori, Isao Takayanagi, Shunsuke Tanaka, Toshinori Otaka, Naoto Yasuda
  • Patent number: 11240448
    Abstract: Provided is a solid-state imaging device. A comparator is configured to perform a first comparing operation of outputting a digital first comparison result signal obtained by processing the overflow charges overflowing from PD1 to FD1 in the storing period, a second comparing operation of outputting a digital second comparison result signal obtained by processing the charges stored in PD1 that are transferred to FD1 in the transfer period, and a third comparing operation of outputting a digital third comparison result signal obtained by processing the charges stored in PD1 that are transferred to FD1 in the transfer period and the charges stored in the charge storing part, and a memory control part controls whether or not to allow writing of the data corresponding to the third comparison result signal into a memory part, depending on the states of the first and second comparison result signals.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: February 1, 2022
    Assignee: BRILLNICS SINGAPORE PTE. LTD.
    Inventors: Kazuya Mori, Toshinori Otaka, Isao Takayanagi
  • Patent number: 11050966
    Abstract: In a solid-state imaging device 10, the first binning switch 81 is formed such that a MOS capacitance and a wire capacitance of a wire connected to the binning switch 81, each having a value in accordance with an ON or OFF state, are added to a capacitance of a floating diffusion FD of a pixel PXL to be read, so as to optimize the capacitance of the floating diffusion FD and optimally adjust a conversion gain in accordance with a mode. This operation increases an image quality.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: June 29, 2021
    Assignee: BRILLNICS SINGAPORE PTE. LTD.
    Inventors: Kazuya Mori, Shunsuke Okura, Isao Takayanagi
  • Publication number: 20200204749
    Abstract: Provided is a solid-state imaging device. A comparator is configured to perform a first comparing operation of outputting a digital first comparison result signal obtained by processing the overflow charges overflowing from PD1 to FD1 in the storing period, a second comparing operation of outputting a digital second comparison result signal obtained by processing the charges stored in PD1 that are transferred to FD1 in the transfer period, and a third comparing operation of outputting a digital third comparison result signal obtained by processing the charges stored in PD1 that are transferred to FD1 in the transfer period and the charges stored in the charge storing part, and a memory control part controls whether or not to allow writing of the data corresponding to the third comparison result signal into a memory part, depending on the states of the first and second comparison result signals.
    Type: Application
    Filed: December 20, 2019
    Publication date: June 25, 2020
    Inventors: Kazuya MORI, Toshinori OTAKA, Isao TAKAYANAGI
  • Patent number: 10694121
    Abstract: A solid-state imaging device, in which a signal holding part can hold a signal with respect to a voltage signal corresponding to an accumulated charge in a photoelectric conversion element of a photodiode PD1 which is transferred to an output node of a floating diffusion FD1 in a transfer period after an integration period and a signal with respect to a voltage signal corresponding to an overflow charge overflowing to the output node of the floating diffusion FD1 from at least the photodiode PD1 in any period among the photoelectric conversion element of the photodiode PD1 and the storage capacity element of the storage capacitor. Due to this, substantially, it becomes possible to realize a broader dynamic range and higher frame rate.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: June 23, 2020
    Assignee: BRILLNICS INC.
    Inventors: Kazuya Mori, Toshinori Otaka, Isao Takayanagi
  • Publication number: 20200162691
    Abstract: In a solid-state imaging device 10, the first binning switch 81 is formed such that a MOS capacitance and a wire capacitance of a wire connected to the binning switch 81, each having a value in accordance with an ON or OFF state, are added to a capacitance of a floating diffusion FD of a pixel PXL to be read, so as to optimize the capacitance of the floating diffusion FD and optimally adjust a conversion gain in accordance with a mode. This operation increases an image quality.
    Type: Application
    Filed: April 11, 2018
    Publication date: May 21, 2020
    Inventors: Kazuya MORI, Shunsuke OKURA, Isao TAKAYANAGI
  • Patent number: 10659709
    Abstract: An AD conversion part has a comparator for performing comparison processing comparing a voltage signal read out by a photoelectric converting and reading part and a reference voltage and outputting a digitalized comparison result signal, the comparator, under the control by a reading part, performs first comparison processing for outputting a digitalized first comparison result signal with respect to a voltage signal corresponding to an overflow charge overflowing from a photodiode PD1 to a floating diffusion FD1 in an integration period and second comparison processing for outputting a digitalized second comparison result signal with respect to a voltage signal corresponding to an accumulated charge of the photodiode PD1 transferred to the floating diffusion FD1 in a transfer period after the integration period. Due to this, it becomes possible to substantially realize a broader dynamic range and higher frame rate.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: May 19, 2020
    Assignee: BRILLNICS INC.
    Inventors: Kazuya Mori, Toshinori Otaka, Isao Takayanagi, Junichi Nakamura, Naoto Yasuda