Abstract: Provided is a liquid ejecting head including: a first board on which a driving element for ejecting liquid is installed; a second board which is installed on the surface of the first board and covers the driving element; a wiring board that includes a first surface on which a wiring, where a driving signal is supplied to the driving element, is formed and a second surface that is at the opposite side to the first surface, and where the first surface of a first end section is joined to the surface of the first board; and a filling material which covers the wiring by being formed at least between the first surface and a wall surface of the second board, in which the height of the filling material with respect to the surface of the first board is high at the first surface side in comparison to the second surface side.

Abstract: Provided is a liquid ejecting head including: a first board on which a driving element for ejecting liquid is installed; a second board which is installed on the surface of the first board and covers the driving element; a wiring board that includes a first surface on which a wiring, where a driving signal is supplied to the driving element, is formed and a second surface that is at the opposite side to the first surface, and where the first surface of a first end section is joined to the surface of the first board; and a filling material which covers the wiring by being formed at least between the first surface and a wall surface of the second board, in which the height of the filling material with respect to the surface of the first board is high at the first surface side in comparison to the second surface side.

Abstract: A liquid ejecting head includes a nozzle plate that has a transparent property and includes a nozzle row in which a plurality of nozzle openings ejecting liquids are arranged in line, and a communicating path forming substrate that is bonded to the nozzle plate and has a communicating path communicating with the nozzle openings, wherein on a surface of one of the communicating path forming substrate and the nozzle plate bonded to a surface of the other thereof, a mark for identifying a nozzle opening as a reference for positioning is formed in the vicinity of the nozzle opening as a reference for positioning among the nozzle openings.

Abstract: Programmable logical blocks (3a to 3c) selected from a block library including information of a plurality of types of programmable logical blocks are disposed in a core region of a semiconductor integrated circuit (100). The degree of freedom of designing a field programmable gate array (FPGA) and the degree of integration are increased. A logic LSI is permitted to have redundancy to flexibly cope with design changes. This affords reduction in develop period and develop costs.

Abstract: A register circuit an arithmetic circuit a register circuit and a logic circuit form a bit slice cell corresponding to a path of propagation connecting the circuits in this order. Similarly, an arithmetic circuit register circuits and a logic circuit form a bit slice cell and an arithmetic circuit register circuits and a logic circuit form a bit slice cell. The bit slice cells are arranged generally in parallel to form a bit slice circuit which prevents redundant lines for connecting the functional circuits, whereby the bit slice circuit is developed in a short period without a decreased degree of integration and prolonged delay time.

Abstract: A method of manufacturing a plurality of integrated circuit devices includes the steps as follows. First, a predetermined plurality number of bonding pads (11, 21) in a predetermined geometry are formed on the surface of each of a plural number of substrate (10, 20). Next, circuits (12, 22) having different signal processing functions respectively are formed in regions of the substrates (10, 20) not occupied by the bonding pads (11, 21), and then, input/output terminals of the circuits (12, 22) are interconnected to respective ones of the bonding pads (11, 21). According to such a manufacturing method of integrated circuit devices, it is possible to employ common devices for wafer test and the same packages for incorporating, and thus reduce production cost and development cost, in case of small quantity production of various types.

Abstract: In designing a layout of a semiconductor integrated circuit device having a large scale circuit block and logic circuit elements provided together, a power supply connecting line is formed rectilinearly to increase the integration density, reduce power supply noise and achieve automation of layout and interconnection. The semiconductor integrated circuit device includes one large scale circuit block and a plurality of logic circuit elements. VDD and GND annular power supply interconnecting lines are provided to surround the large scale circuit block. The annular power supply interconnecting lines extending in the lateral direction are divided into two lines to be disposed, respectively. Connection of the logic circuit elements and the annular power supply interconnecting lines are made by rectilinear VDD and GND power supply branch interconnecting lines.