Abstract: A system includes a first device and a second device coupled to a link. The first device is to transmit one or more request frames for synchronization of a data layer, each request frame including a quantity of bits and an error code. The second device is to receive a first set of bits corresponding to the quantity of bits in each request frame. The second device is to perform an error decode operation on the first set of bits using a first portion of the first set of bits and determine the first set of bits correspond to a frame boundary of the one more request frames responsive to a success of the error decode operation. The second device is to transmit an acknowledgement of the synchronization of the data layer based on determining the first set of bits corresponds to the frame boundary.

Abstract: A system includes a first device and a second device coupled to a link having one or more paths associated with transmitting a clock signal. The first device is to transmit a set of bits associated with a pattern via the one more paths. The set of bits are transmitted using a first clock signal having a first frequency less than a second frequency associated with data transmission operations. The second device is to receive the set of bits associated with the pattern, determine a number of pulses associated with the set of bits over a first period, and determine the number of pulses, associated with the set of bits, satisfies a predetermined condition relating to the number of pulses for the first period. The second device is to initiate a training of the link in response to determining the number of pulses satisfies the predetermined condition.

Abstract: A system includes a first device and a second device coupled to a link. The first device is to transmit one or more request frames for synchronization of a data layer, each request frame including a quantity of bits and an error code. The second device is to receive a first set of bits corresponding to the quantity of bits in each request frame. The second device is to perform an error decode operation on the first set of bits using a first portion of the first set of bits and determine the first set of bits correspond to a frame boundary of the one more request frames responsive to a success of the error decode operation. The second device is to transmit an acknowledgement of the synchronization of the data layer based on determining the first set of bits corresponds to the frame boundary.

Abstract: A microelectronic package has an IC chip that includes logical circuitry for routing certain I/O signals to debug ports disposed on an outer surface of the microelectronic package. The I/O signals include data and command signals that are transmitted between semiconductor chips in the microelectronic package via conductive traces that are not physically accessible via with conventional debugging techniques. The logical circuitry may be configured to programmably select I/O signals based on a software input, and may be connected to the various I/O signals transmitted between the IC chip and another IC chip in the microelectronic package when a debugging of the I/O signals is enabled. Circuitry employed in conventional operation of the IC chip may also be employed to connect the logical circuitry to the various I/O signals.

Abstract: A microelectronic package has an IC chip that includes logical circuitry for routing certain I/O signals to debug ports disposed on an outer surface of the microelectronic package. The I/O signals include data and command signals that are transmitted between semiconductor chips in the microelectronic package via conductive traces that are not physically accessible via with conventional debugging techniques. The logical circuitry may be configured to programmably select I/O signals based on a software input, and may be connected to the various I/O signals transmitted between the IC chip and another IC chip in the microelectronic package when a debugging of the I/O signals is enabled. Circuitry employed in conventional operation of the IC chip may also be employed to connect the logical circuitry to the various I/O signals.