Abstract: An electronic system is disposed on a single integrated circuit including a plurality of power domains and a power control manager. Each power domain may be independently powered. The power control manager includes a set of control registers storing individual control bits, a power switch for each power domain and a programmable microprocessor. The programmable microprocessor controls the digital state of individual bits within the control registers thereby controlling the ON and OFF state of the corresponding power domain.

Abstract: An integrated circuit (IC) includes a plurality of input/output (I/O) terminals through which signals pass into or out of the IC and an I/O timing module. The I/O timing module is configured to add propagation delay to signals passing between the I/O terminals and I/O subsystems of the IC. The I/O timing module includes a plurality of delay elements associated with each of the I/O terminals, a control register associated with each of the I/O terminals, a memory, and I/O delay control logic. The control register is coupled to each of the delay elements associated with the I/O terminal. The memory is encoded with delay information. The I/O delay control logic is configured to initialize the propagation delay associated with each of the I/O terminals by selecting which of the delay elements are to be applied to produce the propagation delay based on the delay information stored in the memory.

Abstract: An integrated circuit (IC) includes a plurality of input/output (I/O) terminals through which signals pass into or out of the IC and an I/O timing module. The I/O timing module is configured to add propagation delay to signals passing between the I/O terminals and I/O subsystems of the IC. The I/O timing module includes a plurality of delay elements associated with each of the I/O terminals, a control register associated with each of the I/O terminals, a memory, and I/O delay control logic. The control register is coupled to each of the delay elements associated with the I/O terminal. The memory is encoded with delay information. The I/O delay control logic is configured to initialize the propagation delay associated with each of the I/O terminals by selecting which of the delay elements are to be applied to produce the propagation delay based on the delay information stored in the memory.